EPM7128AETI100-7 vs EPM7128AET1100-7 Comparaison
Comparaison détaillée côte à côte de EPM7128AETI100-7 par Altera et EPM7128AET1100-7 par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Altera
EPM7128AETI100-7 - MAX 7000A CPLD, 128 Macrocells, 100-TQFP | Altera
EPM7128AETI100-7 ObsoleteComparaison des spécifications
| Paramètre | EPM7128AETI100-7 | EPM7128AET1100-7 |
|---|---|---|
| Marque | Altera | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Dernier achat |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $30,10 | $16,40 |
| Family | MAX 7000A | MAX 7000A (MAX 7000AE) |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Macrocells | 128 | 128 |
| Usable Gates | 2,500 | 2,500 |
| User I/Os | 84 | — |
| Logic Blocks (LABs) | 8 | — |
| Pin-to-Pin Delay (tPD) | 7.5 ns | — |
| Maximum Counter Frequency | 129.9 MHz | — |
| Supply Voltage - Core (VCCINT) | 3.3 V | — |
| I/O Bank Supply (VCCIO) | 2.5 V / 3.3 V / 5 V (MultiVolt) | — |
| Configuration Memory | EEPROM (non-volatile, in-system programmable) | EEPROM (non-volatile, instant-on) |
| JTAG Support | Yes (IEEE 1149.1 boundary-scan) | — |
| Global Clock Inputs | 4 dedicated | — |
| Boîtier | 100-pin TQFP (1.0 mm pitch, 14 x 14 mm) | TQFP-100 |
| Température de fonctionnement | -40 C to +85 C (Industrial) | -40C to +85C (industrial) |
| Type de montage | Surface Mount | Surface Mount |
| Statut RoHS | [DATA_NEEDED: confirm RoHS for non-N suffix] | ROHS3 Compliant |
| Lead-Free Version (MPN Suffix) | -N suffix denotes lead-free (e.g., EPM7128AETI100-7N) | — |
| User I/O Pins | — | 84 |
| Logic Elements / LABs | — | [DATA_NEEDED: LAB count for 7128A] |
| Speed Grade | — | -7 (5 ns pin-to-pin) |
| Supply Voltage VCC | — | 5.0 V (typical) |
| I/O Voltage Tolerance | — | 3.3 V / 5.0 V |
| Programming Interface | — | IEEE 1149.1 JTAG / ByteBlaster |
| Niveau MSL | — | 3 (168 hours, per JEDEC J-STD-020) |
| Lead-Free | — | Yes |
| Process Technology | — | CMOS, EEPROM-based |