EPM7128AETI100-7 vs EPM7128AET1100-7 Comparación
Comparación detallada lado a lado de EPM7128AETI100-7 por Altera y EPM7128AET1100-7 por Intel. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Altera
EPM7128AETI100-7 - MAX 7000A CPLD, 128 Macrocells, 100-TQFP | Altera
EPM7128AETI100-7 ObsoleteComparación de especificaciones
| Parámetro | EPM7128AETI100-7 | EPM7128AET1100-7 |
|---|---|---|
| Marca | Altera | Intel |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Última compra |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $30,10 | $16,40 |
| Family | MAX 7000A | MAX 7000A (MAX 7000AE) |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Macrocells | 128 | 128 |
| Usable Gates | 2,500 | 2,500 |
| User I/Os | 84 | — |
| Logic Blocks (LABs) | 8 | — |
| Pin-to-Pin Delay (tPD) | 7.5 ns | — |
| Maximum Counter Frequency | 129.9 MHz | — |
| Supply Voltage - Core (VCCINT) | 3.3 V | — |
| I/O Bank Supply (VCCIO) | 2.5 V / 3.3 V / 5 V (MultiVolt) | — |
| Configuration Memory | EEPROM (non-volatile, in-system programmable) | EEPROM (non-volatile, instant-on) |
| JTAG Support | Yes (IEEE 1149.1 boundary-scan) | — |
| Global Clock Inputs | 4 dedicated | — |
| Encapsulado | 100-pin TQFP (1.0 mm pitch, 14 x 14 mm) | TQFP-100 |
| Temperatura de funcionamiento | -40 C to +85 C (Industrial) | -40C to +85C (industrial) |
| Tipo de montaje | Surface Mount | Surface Mount |
| Estado RoHS | [DATA_NEEDED: confirm RoHS for non-N suffix] | ROHS3 Compliant |
| Lead-Free Version (MPN Suffix) | -N suffix denotes lead-free (e.g., EPM7128AETI100-7N) | — |
| User I/O Pins | — | 84 |
| Logic Elements / LABs | — | [DATA_NEEDED: LAB count for 7128A] |
| Speed Grade | — | -7 (5 ns pin-to-pin) |
| Supply Voltage VCC | — | 5.0 V (typical) |
| I/O Voltage Tolerance | — | 3.3 V / 5.0 V |
| Programming Interface | — | IEEE 1149.1 JTAG / ByteBlaster |
| Nivel MSL | — | 3 (168 hours, per JEDEC J-STD-020) |
| Lead-Free | — | Yes |
| Process Technology | — | CMOS, EEPROM-based |