EPM7128BTC144-7 vs EPM570T144C5N Comparison
Detailed side-by-side comparison of EPM7128BTC144-7 by Altera and EPM570T144C5N by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM7128BTC144-7 | EPM570T144C5N |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Nrnd | Active |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $9.85 | $9.35 |
| Family | MAX 7000B | MAX II |
| Device Type | CPLD (Complex Programmable Logic Device) | β |
| Macro Cells | 128 | β |
| Usable Gates | 2,500 | β |
| Logic Array Blocks (LABs) | 8 | β |
| User I/O Pins | 100 (per 144-pin TQFP package) | β |
| Pin-to-Pin Delay (tPD) | 7.5 ns | β |
| Maximum Counter Frequency (fCNT) | 126.6 MHz | β |
| Maximum Operating Frequency | 175 MHz (family typical) | β |
| Supply Voltage (VCCINT) | 2.5 V | β |
| I/O Bank Voltage (VCCIO) | 2.5 V / 3.3 V / 5.0 V (multiVolt) | β |
| Configuration Memory | EEPROM (non-volatile, ISP) | β |
| Programmability | IEEE 1149.1 JTAG (ISP) | β |
| Operating Temperature (Commercial) | 0C to +90C | β |
| Package | 144-pin TQFP | TQFP-144 (20 Γ 20 mm, 0.5 mm pitch) |
| Mounting Type | Surface Mount | Surface Mount |
| RoHS Status | [DATA_NEEDED: RoHS status] | Compliant |
| Lead-Free | [DATA_NEEDED: lead-free status] | Yes |
| Series | β | MAX II Device |
| Logic Elements (LEs) | β | 570 |
| Macrocells | β | 440 |
| User I/Os | β | 116 |
| Internal User Flash Memory | β | 8 Kbit |
| Global Clocks | β | 4 |
| Process Technology | β | 0.18 Β΅m 6-layer-metal flash |
| Core Voltage (VCCINT) | β | 1.8 V (typical, internally regulated) |
| I/O Voltage (VCCIO) | β | 1.5 V / 1.8 V / 2.5 V / 3.3 V (multi-voltage, per bank) |
| Maximum User I/O Pins | β | 116 |
| Propagation Delay (tPD) | β | 5.5 ns (typical, [DATA_NEEDED: exact speed grade]) |
| Maximum Frequency (fMAX) | β | 201.1 MHz |
| Operating Temperature | β | 0 Β°C to +85 Β°C (commercial, C5 grade) |
| Programming Interface | β | IEEE 1149.1 JTAG (in-system programmable) |
| Configuration Storage | β | On-chip non-volatile flash |
| Supported I/O Standards | β | LVCMOS, LVTTL, PCI, LVDS, SSTL (per bank VCCIO) |
| MSL Level | β | 3 (per JEDEC J-STD-020) |
| Design Software | β | Intel Quartus II (MAX II device support) |