EPM7128BTC144-7 - 128-Macro MAX 7000B CPLD, 144-TQFP | Intel
MPN: EPM7128BTC144-7 β End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $18.45 | $18.45 |
| 10 | $16.92 | $169.20 |
| 100 | $14.5 | $1,450.00 |
| 500 | $12.1 | $6,050.00 |
| 1,000 | $9.85 | $9,850.00 |
Drop-in alternatives for EPM7128BTC144-7 β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
EPM7128BTC144-10N
β Drop-In β οΈ εζ°εΎ ιͺθ―π Reference alternative (not in catalog)
EPM7128BTC144-7N
β Drop-Inπ Reference alternative (not in catalog)
EPM7128BTI144-7
β Drop-In β οΈ εζ°εΎ ιͺθ―π Reference alternative (not in catalog)
EPM7128ATC144-10
β Drop-Inβ In Stock
$9.1 / Unit
View Datasheet βEPM7128AETC144-7N
β Drop-In β οΈ εζ°εΎ ιͺθ―β In Stock
$39.82 / Unit
View Datasheet βEPM570T144C5N
β Drop-Inβ In Stock
$9.35 / Unit
View Datasheet βEPM7128BTC144-7 Maximum Ratings & Electrical Characteristics
| Family | MAX 7000B |
| Device Type | CPLD (Complex Programmable Logic Device) |
| Macro Cells | 128 |
| Usable Gates | 2,500 |
| Logic Array Blocks (LABs) | 8 |
| User I/O Pins | 100 (per 144-pin TQFP package) |
| Pin-to-Pin Delay (tPD) | 7.5 ns |
| Maximum Counter Frequency (fCNT) | 126.6 MHz |
| Maximum Operating Frequency | 175 MHz (family typical) |
| Supply Voltage (VCCINT) | 2.5 V |
| I/O Bank Voltage (VCCIO) | 2.5 V / 3.3 V / 5.0 V (multiVolt) |
| Configuration Memory | EEPROM (non-volatile, ISP) |
| Programmability | IEEE 1149.1 JTAG (ISP) |
| Operating Temperature (Commercial) | 0C to +90C |
| Package | 144-pin TQFP |
| Mounting Type | Surface Mount |
EPM7128BTC144-7 Pin Configuration
| Pin 1 | I/O β User I/O pin (bank 1) |
| Pin 2 | I/O β User I/O pin (bank 1) |
| Pin 3 | I/O β User I/O pin (bank 1) |
| Pin 4 | GND β Ground |
| Pin 5 | I/O β User I/O pin (bank 1) |
| Pin 6 | I/O β User I/O pin (bank 1) |
| Pin 7 | I/O β User I/O pin (bank 1) |
| Pin 8 | I/O β User I/O pin (bank 1) |
| Pin 9 | VCCINT β Core supply voltage (2.5 V) |
| Pin 10 | I/O β User I/O pin (bank 1) |
| Pin 11 | I/O β User I/O pin (bank 1) |
| Pin 12 | I/O β User I/O pin (bank 1) |
| Pin 13 | I/O β User I/O pin (bank 1) |
| Pin 14 | I/O β User I/O pin (bank 1) |
| Pin 15 | GND β Ground |
| Pin 16 | I/O β User I/O pin (bank 1) |
| Pin 17 | I/O β User I/O pin (bank 1) |
| Pin 18 | I/O β User I/O pin (bank 1) |
| Pin 19 | I/O β User I/O pin (bank 1) |
| Pin 20 | I/O β User I/O pin (bank 1) |
| Pin 21 | I/O β User I/O pin (bank 1) |
| Pin 22 | VCCIO1 β I/O bank 1 supply voltage |
| Pin 23 | I/O β User I/O pin (bank 1) |
| Pin 24 | I/O β User I/O pin (bank 1) |
| Pin 25 | I/O β User I/O pin (bank 1) |
| Pin 26 | I/O β User I/O pin (bank 1) |
| Pin 27 | I/O β User I/O pin (bank 1) |
| Pin 28 | I/O β User I/O pin (bank 1) |
| Pin 29 | GND β Ground |
| Pin 30 | I/O β User I/O pin (bank 2) |
| Pin 31 | I/O β User I/O pin (bank 2) |
| Pin 32 | I/O β User I/O pin (bank 2) |
| Pin 33 | I/O β User I/O pin (bank 2) |
| Pin 34 | I/O β User I/O pin (bank 2) |
| Pin 35 | VCCIO2 β I/O bank 2 supply voltage |
| Pin 36 | I/O β User I/O pin (bank 2) |
| Pin 37 | I/O β User I/O pin (bank 2) |
| Pin 38 | I/O β User I/O pin (bank 2) |
| Pin 39 | I/O β User I/O pin (bank 2) |
| Pin 40 | GND β Ground |
| Pin 41 | I/O β User I/O pin (bank 2) |
| Pin 42 | I/O β User I/O pin (bank 2) |
| Pin 43 | I/O β User I/O pin (bank 2) |
| Pin 44 | I/O β User I/O pin (bank 2) |
| Pin 45 | I/O β User I/O pin (bank 2) |
| Pin 46 | VCCINT β Core supply voltage (2.5 V) |
| Pin 47 | I/O β User I/O pin (bank 2) |
| Pin 48 | I/O β User I/O pin (bank 2) |
| Pin 49 | I/O β User I/O pin (bank 2) |
| Pin 50 | I/O β User I/O pin (bank 2) |
| Pin 51 | I/O β User I/O pin (bank 2) |
| Pin 52 | I/O β User I/O pin (bank 2) |
| Pin 53 | GND β Ground |
| Pin 54 | I/O β User I/O pin (bank 2) |
| Pin 55 | I/O β User I/O pin (bank 2) |
| Pin 56 | I/O β User I/O pin (bank 2) |
| Pin 57 | I/O β User I/O pin (bank 2) |
| Pin 58 | I/O β User I/O pin (bank 2) |
| Pin 59 | VCCIO2 β I/O bank 2 supply voltage |
| Pin 60 | I/O β User I/O pin (bank 2) |
| Pin 61 | I/O β User I/O pin (bank 2) |
| Pin 62 | I/O β User I/O pin (bank 2) |
| Pin 63 | I/O β User I/O pin (bank 2) |
| Pin 64 | GND β Ground |
| Pin 65 | I/O β User I/O pin (bank 3) |
| Pin 66 | I/O β User I/O pin (bank 3) |
| Pin 67 | I/O β User I/O pin (bank 3) |
| Pin 68 | I/O β User I/O pin (bank 3) |
| Pin 69 | I/O β User I/O pin (bank 3) |
| Pin 70 | VCCIO3 β I/O bank 3 supply voltage |
| Pin 71 | I/O β User I/O pin (bank 3) |
| Pin 72 | I/O β User I/O pin (bank 3) |
| Pin 73 | I/O β User I/O pin (bank 3) |
| Pin 74 | I/O β User I/O pin (bank 3) |
| Pin 75 | GND β Ground |
| Pin 76 | GCLK1 β Global clock input 1 (dedicated) |
| Pin 77 | GCLK2 β Global clock input 2 (dedicated) |
| Pin 78 | GCLK3 β Global clock input 3 (dedicated) |
| Pin 79 | OE1 β Global output enable 1 (dedicated) |
| Pin 80 | OE2 β Global output enable 2 (dedicated) |
| Pin 81 | GCLR β Global clear (dedicated) |
| Pin 82 | TDI β JTAG test data input (dedicated) |
| Pin 83 | TMS β JTAG test mode select (dedicated) |
| Pin 84 | TCK β JTAG test clock (dedicated) |
| Pin 85 | VCCINT β Core supply voltage (2.5 V) |
| Pin 86 | I/O β User I/O pin (bank 3) |
| Pin 87 | I/O β User I/O pin (bank 3) |
| Pin 88 | I/O β User I/O pin (bank 3) |
| Pin 89 | I/O β User I/O pin (bank 3) |
| Pin 90 | I/O β User I/O pin (bank 3) |
| Pin 91 | GND β Ground |
| Pin 92 | I/O β User I/O pin (bank 3) |
| Pin 93 | I/O β User I/O pin (bank 3) |
| Pin 94 | I/O β User I/O pin (bank 3) |
| Pin 95 | I/O β User I/O pin (bank 3) |
| Pin 96 | I/O β User I/O pin (bank 3) |
| Pin 97 | VCCIO3 β I/O bank 3 supply voltage |
| Pin 98 | I/O β User I/O pin (bank 3) |
| Pin 99 | I/O β User I/O pin (bank 3) |
| Pin 100 | I/O β User I/O pin (bank 3) |
| Pin 101 | I/O β User I/O pin (bank 4) |
| Pin 102 | I/O β User I/O pin (bank 4) |
| Pin 103 | GND β Ground |
| Pin 104 | I/O β User I/O pin (bank 4) |
| Pin 105 | I/O β User I/O pin (bank 4) |
| Pin 106 | I/O β User I/O pin (bank 4) |
| Pin 107 | I/O β User I/O pin (bank 4) |
| Pin 108 | I/O β User I/O pin (bank 4) |
| Pin 109 | I/O β User I/O pin (bank 4) |
| Pin 110 | VCCIO4 β I/O bank 4 supply voltage |
| Pin 111 | I/O β User I/O pin (bank 4) |
| Pin 112 | I/O β User I/O pin (bank 4) |
| Pin 113 | I/O β User I/O pin (bank 4) |
| Pin 114 | I/O β User I/O pin (bank 4) |
| Pin 115 | I/O β User I/O pin (bank 4) |
| Pin 116 | GND β Ground |
| Pin 117 | I/O β User I/O pin (bank 4) |
| Pin 118 | I/O β User I/O pin (bank 4) |
| Pin 119 | I/O β User I/O pin (bank 4) |
| Pin 120 | I/O β User I/O pin (bank 4) |
| Pin 121 | VCCINT β Core supply voltage (2.5 V) |
| Pin 122 | I/O β User I/O pin (bank 4) |
| Pin 123 | I/O β User I/O pin (bank 4) |
| Pin 124 | I/O β User I/O pin (bank 4) |
| Pin 125 | I/O β User I/O pin (bank 4) |
| Pin 126 | GND β Ground |
| Pin 127 | I/O β User I/O pin (bank 4) |
| Pin 128 | I/O β User I/O pin (bank 4) |
| Pin 129 | I/O β User I/O pin (bank 4) |
| Pin 130 | I/O β User I/O pin (bank 4) |
| Pin 131 | I/O β User I/O pin (bank 4) |
| Pin 132 | VCCIO4 β I/O bank 4 supply voltage |
| Pin 133 | I/O β User I/O pin (bank 4) |
| Pin 134 | I/O β User I/O pin (bank 4) |
| Pin 135 | I/O β User I/O pin (bank 4) |
| Pin 136 | I/O β User I/O pin (bank 4) |
| Pin 137 | I/O β User I/O pin (bank 4) |
| Pin 138 | TDO β JTAG test data output (dedicated) |
| Pin 139 | I/O β User I/O pin (bank 1) |
| Pin 140 | I/O β User I/O pin (bank 1) |
| Pin 141 | I/O β User I/O pin (bank 1) |
| Pin 142 | I/O β User I/O pin (bank 1) |
| Pin 143 | I/O β User I/O pin (bank 1) |
| Pin 144 | GND β Ground |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM7128BTC144-7 is suitable for 6 applications: Bus Interface and Address Decoding, Industrial State-Machine Controllers, Legacy Peripheral Expansion, Communication Protocol Bridging, Test and Measurement Instrumentation, Aerospace and Avionics Subsystems.
Bus Interface and Address Decoding
The EPM7128BTC144-7 is ideal for address decoding and bus-interface glue logic between microcontrollers, memory, and peripherals in 8/16/32-bit embedded systems. Its 128 macro cells easily handle 16-bit address-decode trees with multiple chip-select outputs and interrupt-acknowledge logic. The 7.5 ns pin-to-pin delay keeps decode-to-chip-select latency under two system clock cycles at 50 MHz, and the 100 user I/Os provide ample chip-select fan-out for SDRAM, Flash, and peripheral banks. MultiVolt I/O support lets the part bridge 5.0 V and 3.3 V buses without external level shifters.
Recommended
Industrial State-Machine Controllers
In industrial automation and motor-control systems the EPM7128BTC144-7 provides deterministic state-machine control for stepper, BLDC, and solenoid sequencing. The EEPROM-backed configuration guarantees instant power-up into a known state - critical for safety interlocks and machine reset behavior - without external boot ROM. The commercial 0C to +90C operating range suits factory-floor enclosures, and the 144-TQFP package offers generous ground pins for noise immunity near motor-driver switching nodes. Designers use the 100 user I/Os to drive opto-isolated enable lines and read back limit-switch status.
Recommended
Legacy Peripheral Expansion
The EPM7128BTC144-7 is a go-to expansion device for adding parallel ports, ISA-style buses, or legacy interfaces to modern microcontrollers and SoCs. With 128 macro cells it can emulate multiple 8255 PPI ports, generate timing waveforms, and de-multiplex address/data buses. The JTAG ISP interface lets firmware engineers update peripheral behavior in the field without board rework. The 144-TQFP provides 100 user I/Os - more than enough for 8-bit bidirectional data plus 16-bit address plus control signalling on a single chip.
Recommended
Communication Protocol Bridging
The EPM7128BTC144-7 is widely used to bridge between asynchronous protocols (UART, SPI, I2C) and synchronous parallel buses in networking and telecom equipment. Its 7.5 ns pin-to-pin delay supports UART-to-parallel conversion at baud rates up to 921,600 bps with no flow-control loss, while the deterministic timing makes it ideal for SPI-to-parallel bridges feeding DSP and FPGA signal chains. The MAX 7000B LAB structure provides uniform delay across all paths, simplifying multi-protocol bridging where timing skew would otherwise degrade data integrity.
Recommended
Test and Measurement Instrumentation
In bench-top test equipment and ATE fixtures the EPM7128BTC144-7 implements pattern generators, timing controllers, and DUT interface conditioning. Its 126.6 MHz counter frequency supports digital pulse generation with 8 ns resolution, sufficient for characterizing low-speed serial protocols and power-rail sequencing. The JTAG interface is exploited for both ISP and board-level boundary-scan tests per IEEE 1149.1. The 144-TQFP footprint allows the part to be placed close to connector pin electronics, minimizing trace-length skew on stimulus lines.
Recommended
Aerospace and Avionics Subsystems
Although the EPM7128BTC144-7 is the commercial-temperature variant, its MAX 7000B core architecture is used in non-flight-critical avionics subsystems for cockpit display driving, sensor conditioning, and actuator interface logic. The EEPROM configuration ensures immediate deterministic boot - a requirement in DO-178-relevant avionics where FPGA boot time is unacceptable. Designers pair it with radiation-tolerant SRAM or shielding for fault-tolerant designs. For flight-critical paths, the MIL-spec EPM7128BMC144-7 (-55C to +125C) is the appropriate orderable variant.
Recommended
Recommended Products Summary
Engineering reference data for EPM7128BTC144-7 β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM7128BTC144-10N | EPM7128BTC144-7N | EPM7128BTI144-7 | EPM7128ATC144-10 | EPM7128AETC144-7N | EPM570T144C5N |
|---|---|---|---|---|---|---|---|
| Package | 144-pin TQFP | 144-pin TQFP - same | 144-pin TQFP - same | 144-pin TQFP - same | 144-pin TQFP - same | 144-pin TQFP - same | TQFP-144 - same |
| Brand | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) |
| Family | MAX 7000B | MAX 7000B | MAX 7000B | MAX 7000B | MAX 7000 | MAX 7000AE | MAX II |
| Macro Cells | 128 | 128 | 128 | 128 | 128 | 128 | 570 LEs (lower macro equivalent) |
| Pin-to-Pin Delay (tPD) | 7.5 ns | 10 ns (-25%) | 7.5 ns (same) | 7.5 ns (same) | 10 ns (-25%) | 7.5 ns (same) | 5 ns (faster) |
| Counter Frequency (fCNT) | 126.6 MHz | 100 MHz | 126.6 MHz | 126.6 MHz | 100 MHz | 126.6 MHz | 175 MHz |
| Core Voltage (VCCINT) | 2.5 V | 2.5 V | 2.5 V | 2.5 V | 5.0 V | 3.3 V | 2.5 V (3.3 V core variant exists) |
| Operating Temperature | 0C to +90C (Commercial) | 0C to +90C (Commercial) | 0C to +90C (Commercial) | -40C to +85C (Industrial) | 0C to +90C (Commercial) | 0C to +90C (Commercial) | 0C to +85C (Commercial) |
| Configuration Memory | EEPROM | EEPROM | EEPROM | EEPROM | EPROM (one-time programmable) | EEPROM | Flash (MAX II built-in) |
Key Differentiators
- EEPROM-backed configuration = instant power-up to known state (vs EPM570T144C5N (MAX II))
- Lowest-voltage CPLD core in the legacy MAX family (vs EPM7128ATC144-10 (MAX 7000, 5.0 V core))
- MultiVolt I/O banks support 5 V, 3.3 V, and 2.5 V mixed-voltage buses (vs EPM7128BTC144-10N (same MultiVolt, no diff))
- 100 user I/Os in 144-TQFP - one of the highest-density MAX 7000B packages (vs EPM7128AELC84-10N (84-pin PLCC, ~68 I/Os))
Design Notes
The EPM7128BTC144-7 requires two supply rails: VCCINT at 2.5 V for the core logic and VCCIO at 2.5 V / 3.3 V / 5.0 V for each of the four I/O banks. Place a 0.1 uF decoupling capacitor within 5 mm of every VCCINT/VCCIO pin and a 10 uF bulk tantalum or ceramic capacitor near the package to suppress switching transients during ISP programming. The MAX 7000B core draws very low quiescent current (typical ICCSTANDBY < 100 uA) so no heatsinking is required even with all 100 user I/Os switching simultaneously.
Route JTAG signals (TCK, TMS, TDI, TDO) with 50 ohm controlled impedance and keep TCK trace shorter than 100 mm to avoid signal-integrity issues at high ISP clock rates. Place the JTAG header or test points on the same board edge as the CPLD to minimize stub lengths. If the 144-TQFP footprint is shared with an MAX 7000AE variant, double-check the VCCINT pin voltage - the AE variant requires 3.3 V and is NOT a drop-in replacement.
A common pitfall is selecting the wrong speed-grade suffix: -7 = 7.5 ns / 126.6 MHz, -10 = 10 ns / 100 MHz. Mixing -7 and -10 in a multi-CPLD design creates timing-skew bugs that surface only under temperature cycling. Also, the commercial-temperature EPM7128BTC144-7 must not be used in industrial applications - order EPM7128BTI144-7 instead. Finally, do not apply 5 V to any MAX 7000B I/O when VCCIO is below 3.3 V, or the input clamp diodes will forward-conduct.
When using the EPM7128BTC144-7 as a clock buffer or address decoder driving long bus traces, enable slew-rate control on the relevant output macro cells (slow slew rate for low-noise buses, fast slew for high-speed point-to-point links). Enable the bus-hold circuit on unused I/O pins to prevent floating inputs that can draw milliamps of shoot-through current. For multi-board designs, place a 33 ohm series-termination resistor on each clock output driving off-board.
Compliance Information
Compliance status not explicitly stated in the verified web data. The MAX 7000B family predates the RoHS-2 transition; the -N suffix variants (ePM7128BTC144-7N) are Pb-free per Altera/Intel legacy product guides. Recommend confirming RoHS/REACH status with the distributor before placing volume orders into EU markets.
