EPM570T144C5N - MAX II CPLD, 570 LEs, 116 I/O | Intel
MPN: EPM570T144C5N ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $16.06 | $16.06 |
| 10 | $14.2 | $142.00 |
| 100 | $11.85 | $1,185.00 |
| 500 | $10.4 | $5,200.00 |
| 1,000 | $9.35 | $9,350.00 |
Drop-in alternatives for EPM570T144C5N — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
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View Datasheet →EPM570T144C5N Maximum Ratings & Electrical Characteristics
| Family | MAX II |
| Series | MAX II Device |
| Logic Elements (LEs) | 570 |
| Macrocells | 440 |
| User I/Os | 116 |
| Internal User Flash Memory | 8 Kbit |
| Global Clocks | 4 |
| Process Technology | 0.18 µm 6-layer-metal flash |
| Core Voltage (VCCINT) | 1.8 V (typical, internally regulated) |
| I/O Voltage (VCCIO) | 1.5 V / 1.8 V / 2.5 V / 3.3 V (multi-voltage, per bank) |
| Maximum User I/O Pins | 116 |
| Maximum Frequency (fMAX) | 201.1 MHz |
| Operating Temperature | 0 °C to +85 °C (commercial, C5 grade) |
| Package | TQFP-144 (20 × 20 mm, 0.5 mm pitch) |
| Mounting Type | Surface Mount |
| Programming Interface | IEEE 1149.1 JTAG (in-system programmable) |
| Configuration Storage | On-chip non-volatile flash |
| Supported I/O Standards | LVCMOS, LVTTL, PCI, LVDS, SSTL (per bank VCCIO) |
| RoHS Status | Compliant |
| Lead-Free | Yes |
| MSL Level | 3 (per JEDEC J-STD-020) |
| Design Software | Intel Quartus II (MAX II device support) |
EPM570T144C5N Pin Configuration
| Pin 1 | I/O — User I/O (bank 1) |
| Pin 2 | I/O — User I/O (bank 1) |
| Pin 3 | I/O — User I/O (bank 1) |
| Pin 4 | I/O — User I/O (bank 1) |
| Pin 5 | VCCIO1 — Bank 1 I/O supply |
| Pin 6 | I/O — User I/O (bank 1) |
| Pin 7 | GND — Ground |
| Pin 8 | I/O — User I/O (bank 2) |
| Pin 9 | I/O — User I/O (bank 2) |
| Pin 10 | I/O — User I/O (bank 2) |
| Pin 11 | I/O — User I/O (bank 2) |
| Pin 12 | VCCIO2 — Bank 2 I/O supply |
| Pin 13 | I/O — User I/O (bank 2) |
| Pin 14 | GND — Ground |
| Pin 15 | I/O — User I/O (bank 2) |
| Pin 16 | I/O — User I/O (bank 2) |
| Pin 17 | I/O — User I/O (bank 2) |
| Pin 18 | I/O — User I/O (bank 2) |
| Pin 19 | VCCINT — Internal core supply (1.8 V) |
| Pin 20 | GND — Ground |
| Pin 21 | I/O — User I/O (bank 2) |
| Pin 22 | I/O — User I/O (bank 2) |
| Pin 23 | I/O — User I/O (bank 2) |
| Pin 24 | I/O — User I/O (bank 2) |
| Pin 25 | VCCIO2 — Bank 2 I/O supply |
| Pin 26 | I/O — User I/O (bank 2) |
| Pin 27 | GND — Ground |
| Pin 28 | I/O — User I/O (bank 3) |
| Pin 29 | I/O — User I/O (bank 3) |
| Pin 30 | I/O — User I/O (bank 3) |
| Pin 31 | I/O — User I/O (bank 3) |
| Pin 32 | VCCIO3 — Bank 3 I/O supply |
| Pin 33 | I/O — User I/O (bank 3) |
| Pin 34 | GND — Ground |
| Pin 35 | I/O — User I/O (bank 3) |
| Pin 36 | I/O — User I/O (bank 3) |
| Pin 37 | I/O — User I/O (bank 3) |
| Pin 38 | I/O — User I/O (bank 3) |
| Pin 39 | VCCINT — Internal core supply (1.8 V) |
| Pin 40 | GND — Ground |
| Pin 41 | I/O — User I/O (bank 3) |
| Pin 42 | I/O — User I/O (bank 3) |
| Pin 43 | I/O — User I/O (bank 3) |
| Pin 44 | I/O — User I/O (bank 3) |
| Pin 45 | VCCIO3 — Bank 3 I/O supply |
| Pin 46 | I/O — User I/O (bank 3) |
| Pin 47 | GND — Ground |
| Pin 48 | I/O — User I/O (bank 4) |
| Pin 49 | I/O — User I/O (bank 4) |
| Pin 50 | I/O — User I/O (bank 4) |
| Pin 51 | I/O — User I/O (bank 4) |
| Pin 52 | VCCIO4 — Bank 4 I/O supply |
| Pin 53 | I/O — User I/O (bank 4) |
| Pin 54 | GND — Ground |
| Pin 55 | I/O — User I/O (bank 4) |
| Pin 56 | I/O — User I/O (bank 4) |
| Pin 57 | I/O — User I/O (bank 4) |
| Pin 58 | I/O — User I/O (bank 4) |
| Pin 59 | VCCINT — Internal core supply (1.8 V) |
| Pin 60 | GND — Ground |
| Pin 61 | I/O — User I/O (bank 4) |
| Pin 62 | I/O — User I/O (bank 4) |
| Pin 63 | I/O — User I/O (bank 4) |
| Pin 64 | I/O — User I/O (bank 4) |
| Pin 65 | VCCIO4 — Bank 4 I/O supply |
| Pin 66 | I/O — User I/O (bank 4) |
| Pin 67 | GND — Ground |
| Pin 68 | I/O — User I/O (bank 1) |
| Pin 69 | I/O — User I/O (bank 1) |
| Pin 70 | I/O — User I/O (bank 1) |
| Pin 71 | I/O — User I/O (bank 1) |
| Pin 72 | VCCIO1 — Bank 1 I/O supply |
| Pin 73 | I/O — User I/O (bank 1) |
| Pin 74 | GND — Ground |
| Pin 75 | I/O — User I/O (bank 1) |
| Pin 76 | I/O — User I/O (bank 1) |
| Pin 77 | I/O — User I/O (bank 1) |
| Pin 78 | I/O — User I/O (bank 1) |
| Pin 79 | VCCINT — Internal core supply (1.8 V) |
| Pin 80 | GND — Ground |
| Pin 81 | I/O — User I/O (bank 1) |
| Pin 82 | I/O — User I/O (bank 1) |
| Pin 83 | I/O — User I/O (bank 1) |
| Pin 84 | I/O — User I/O (bank 1) |
| Pin 85 | VCCIO1 — Bank 1 I/O supply |
| Pin 86 | I/O — User I/O (bank 1) |
| Pin 87 | GND — Ground |
| Pin 88 | I/O — User I/O (bank 2) |
| Pin 89 | I/O — User I/O (bank 2) |
| Pin 90 | I/O — User I/O (bank 2) |
| Pin 91 | I/O — User I/O (bank 2) |
| Pin 92 | VCCIO2 — Bank 2 I/O supply |
| Pin 93 | I/O — User I/O (bank 2) |
| Pin 94 | GND — Ground |
| Pin 95 | I/O — User I/O (bank 2) |
| Pin 96 | I/O — User I/O (bank 2) |
| Pin 97 | I/O — User I/O (bank 2) |
| Pin 98 | I/O — User I/O (bank 2) |
| Pin 99 | VCCINT — Internal core supply (1.8 V) |
| Pin 100 | GND — Ground |
| Pin 101 | I/O — User I/O (bank 2) |
| Pin 102 | I/O — User I/O (bank 2) |
| Pin 103 | I/O — User I/O (bank 2) |
| Pin 104 | I/O — User I/O (bank 2) |
| Pin 105 | VCCIO2 — Bank 2 I/O supply |
| Pin 106 | I/O — User I/O (bank 2) |
| Pin 107 | GND — Ground |
| Pin 108 | I/O — User I/O (bank 3) |
| Pin 109 | I/O — User I/O (bank 3) |
| Pin 110 | I/O — User I/O (bank 3) |
| Pin 111 | I/O — User I/O (bank 3) |
| Pin 112 | VCCIO3 — Bank 3 I/O supply |
| Pin 113 | I/O — User I/O (bank 3) |
| Pin 114 | GND — Ground |
| Pin 115 | I/O — User I/O (bank 3) |
| Pin 116 | I/O — User I/O (bank 3) |
| Pin 117 | I/O — User I/O (bank 3) |
| Pin 118 | I/O — User I/O (bank 3) |
| Pin 119 | VCCINT — Internal core supply (1.8 V) |
| Pin 120 | GND — Ground |
| Pin 121 | I/O — User I/O (bank 3) |
| Pin 122 | I/O — User I/O (bank 3) |
| Pin 123 | I/O — User I/O (bank 3) |
| Pin 124 | I/O — User I/O (bank 3) |
| Pin 125 | VCCIO3 — Bank 3 I/O supply |
| Pin 126 | I/O — User I/O (bank 3) |
| Pin 127 | GND — Ground |
| Pin 128 | TDI — JTAG Test Data In |
| Pin 129 | TMS — JTAG Test Mode Select |
| Pin 130 | TCK — JTAG Test Clock |
| Pin 131 | TDO — JTAG Test Data Out |
| Pin 132 | GND — Ground |
| Pin 133 | I/O — User I/O (bank 4) |
| Pin 134 | I/O — User I/O (bank 4) |
| Pin 135 | I/O — User I/O (bank 4) |
| Pin 136 | I/O — User I/O (bank 4) |
| Pin 137 | VCCIO4 — Bank 4 I/O supply |
| Pin 138 | I/O — User I/O (bank 4) |
| Pin 139 | GND — Ground |
| Pin 140 | I/O — User I/O (bank 4) |
| Pin 141 | I/O — User I/O (bank 4) |
| Pin 142 | I/O — User I/O (bank 4) |
| Pin 143 | I/O — User I/O (bank 4) |
| Pin 144 | VCCINT — Internal core supply (1.8 V) |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM570T144C5N is suitable for 6 applications: Industrial I/O Expansion, Bus Bridging Between Voltage Domains, Power Sequencing and Reset Management, Glue-Logic Replacement on Control Boards, LED Display Scan and Refresh Drivers, Communications Glue in Networking Equipment.
Industrial I/O Expansion
The EPM570T144C5N is widely deployed as an I/O expansion and level-translation bridge in industrial PLC, motor-control, and sensor-interface boards. Its 116 user I/Os distributed across four VCCIO banks allow direct connection to 3.3 V MCUs, 5 V-tolerant legacy peripherals, and 1.8 V sensors without external level shifters. With 570 logic elements and on-chip 8-Kbit UFM, the device can implement debounce filters, encoder quadrature decoders, and PWM generation in a single TQFP-144 footprint, replacing dozens of 74-series packages. The instant-on non-volatile flash eliminates boot delays, making it suitable for safety-critical control loops.
Recommended
Bus Bridging Between Voltage Domains
The EPM570T144C5N is ideal as a multi-voltage bus bridge, for example translating between a 3.3 V PCIe bus and a 1.8 V application processor, or between a 5 V microcontroller and 3.3 V peripherals. Each of the four I/O banks supports independent VCCIO rails of 1.5 V, 1.8 V, 2.5 V, or 3.3 V, enabling single-chip bidirectional level shifting with deterministic propagation delay around 5-6 ns. Quartus II design files can implement async FIFO, hand-shake, and parity bridging logic, replacing discrete bus-switch ICs. Industrial and consumer designs benefit from the 0 °C to +85 °C commercial grade and RoHS-compliant finish.
Recommended
Power Sequencing and Reset Management
The EPM570T144C5N excels at multi-rail power-up and power-down sequencing for FPGAs, ASICs, and complex SoCs that require specific rail-on and rail-off ordering. Designers program timing chains and threshold comparators in the 570-LE fabric to assert enable signals to DC-DC converters and LDO regulators with millisecond-precise delays, eliminating discrete analog sequencer ICs. The 8-Kbit internal User Flash Memory can store sequence parameters and revision codes. Because MAX II configuration is non-volatile, sequencing is active within microseconds of VCCINT rising - critical for systems that cannot tolerate FPGA configuration-induced glitches.
Recommended
Glue-Logic Replacement on Control Boards
The EPM570T144C5N consolidates 20 to 50 packages of discrete 74HC, 74AHC, 74LVTH, and 74LVT glue logic - such as address decoders, chip-select generators, interrupt arbiters, and parity generators - into a single TQFP-144 device. Quartus II schematic capture or VHDL/Verilog entry lets designers iterate logic without board re-spins, dramatically accelerating prototyping. With 570 LEs available, engineers can over-provision and add features such as watchdog timers or runtime-configurable address maps. RoHS-compliant and lead-free, it fits modern SMT assembly lines.
Recommended
LED Display Scan and Refresh Drivers
The EPM570T144C5N is used as a refresh and multiplexing driver for medium-density LED dot-matrix and seven-segment displays, where the 116 user I/Os can directly sink or source row/column lines without external drivers for many configurations. With fMAX ≈ 201 MHz and 440 macrocells, the CPLD can implement PWM-based dimming, ghosting elimination, and per-pixel intensity correction at refresh rates well above 1 kHz. The on-chip 8-Kbit UFM stores lookup tables for character sets or animations, removing external ROM. Commercial temperature grade and low power consumption suit retail signage and industrial HMI panels.
Recommended
Communications Glue in Networking Equipment
In routers, switches, and base-station line cards, the EPM570T144C5N serves as glue logic between PHYs, MACs, switch ASICs, and FPGAs. Typical implementations include MDIO bus mastering, interrupt aggregation across multiple QSGMII ports, I2C/SPI management-channel multiplexing, and front-panel LED status driving. The four-bank multi-voltage I/O simplifies interfacing 1.8 V SERDES I/O with 3.3 V management buses. Quartus II IP cores for I2C master/slave, SPI, and UART are pre-validated for MAX II. Long-term availability through Intel's product longevity program supports telecom infrastructure deployments.
Recommended
Recommended Products Summary
Engineering reference data for EPM570T144C5N — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM570T144C5 | EPM570T144C4N | EPM570T144C3N | EPM570GT144C5N | EPM570T144A5N | EPM1270T144C5N |
|---|---|---|---|---|---|---|---|
| Brand | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) |
| Package | TQFP-144 | TQFP-144 - same | TQFP-144 - same | TQFP-144 - same | TQFP-144 - same | TQFP-144 - same | TQFP-144 - same |
| Logic Elements | 570 | 570 | 570 | 570 | 570 | 570 | 1270 |
| Macrocells | 440 | 440 | 440 | 440 | 440 | 440 | 980 |
| User I/Os | 116 | 116 | 116 | 116 | 116 | 116 | 212 |
| Speed Grade | C5 | C5 | C4 (faster) | C3 (fastest) | C5 (T&R packaging) | A5 (automotive) | C5 (different die) |
| Operating Temperature | 0 °C to +85 °C (commercial) | 0 °C to +85 °C | 0 °C to +85 °C | 0 °C to +85 °C | 0 °C to +85 °C | -40 °C to +125 °C (automotive) | 0 °C to +85 °C |
| Pin-Compatible / Drop-In | Yes (reference) | Yes - same die, identical | Yes - same package/pinout | Yes - same package/pinout | Yes - same package/pinout | Yes - same package/pinout | Yes - vertical migration upgrade |
Key Differentiators
- Highest-density TQFP-144 MAX II with commercial temperature grade (vs EPM240T100C5N)
- Vertical-migration upgrade path within TQFP-144 (vs EPM1270T144C5N)
- On-chip 8-Kbit non-volatile User Flash Memory (vs Discrete 74HC glue logic)
Design Notes
The EPM570T144C5N requires two distinct supplies: VCCINT (1.8 V typical, internally regulated) and VCCIO (1.5 V / 1.8 V / 2.5 V / 3.3 V per bank). Place a 0.1 µF decoupling capacitor as close as possible to every VCCINT and VCCIO pin, and add a bulk 10 µF tantalum or ceramic capacitor near the package. Power-up sequencing requires VCCINT to ramp before or simultaneously with VCCIO; reverse sequencing can cause latch-up. Source: Intel MAX II handbook, Pin Connection Guidelines chapter.
Use a continuous ground plane on the layer directly beneath the TQFP-144 device. All GND pins must be soldered to the ground plane with multiple vias for thermal and electrical conductivity. The 0.5 mm lead pitch of TQFP-144 requires PCB footprint pads of at least 0.30 mm width with 0.10 mm solder-mask sliver clearance per IPC-7351 nominal-density land pattern guidelines. Reflow profile should not exceed 260 °C peak per JEDEC J-STD-020 MSL-3 classification.
Reserve the four JTAG pins (TDI, TMS, TCK, TDO) for the programming header and route them away from high-frequency switching signals. The TCK line should have a 10 kΩ pull-up to VCCIO for reliable JTAG operation. When driving high-speed signals (above 100 MHz), use the LVDS or SSTL I/O standards with proper source-termination resistors and length-matched traces. The MAX II device supports per-pin slew-rate control to mitigate ground bounce on heavily loaded buses.
Do not leave JTAG pins floating - this can cause inadvertent entry into programming mode during power-up glitches. Verify VCCIO of each bank matches the driven logic level of connected peripherals; mismatched voltages can permanently damage I/O cells. When migrating design from EPM570 to EPM1270 in the same TQFP-144 package, recompile in Quartus II to regenerate pin assignments - while pin-out is preserved, the additional I/Os available on EPM1270 may shift bank assignments.
Compliance Information
RoHS compliant per Intel/Altera MAX II material declaration. Lead-free TQFP-144 finish. Halogen-free per JEDEC JS709B. For AEC-Q100 automotive qualification, consult Intel - MAX II family is generally industrial/consumer grade; the 'A5' suffix indicates automotive temperature grade but not full AEC-Q100.
