EPM7128ELC84-12 vs EPM7128SLC8410 Comparison
Detailed side-by-side comparison of EPM7128ELC84-12 by Altera and EPM7128SLC8410 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM7128ELC84-12
EPM7128ELC84-12 - 128-Macrocell MAX 7000 CPLD, 12ns, 84-PLCC
EPM7128ELC84-12 ObsoleteSpecification Comparison
| Parameter | EPM7128ELC84-12 | EPM7128SLC8410 |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $10.40 | $9.75 |
| Family | MAX 7000 (MAX 7000E series) | MAX 7000S |
| Logic Family | CMOS, EEPROM-based | β |
| Usable Gates | 2,500 | β |
| Macrocells | 128 | 128 |
| Logic Array Blocks (LABs) | 8 | β |
| User I/Os | 84 | β |
| Propagation Delay (tpd1) | 12 ns | β |
| Internal Global Clock Frequency | 90.9 MHz | β |
| Setup Time | 4.5 ns | β |
| Supply Voltage (VCCINT / VCCIO) | 5 V (4.75 V to 5.25 V) | β |
| Operating Temperature | 0C to +70C (commercial) | 0C to +70C (commercial) |
| Package | 84-pin PLCC (J-Lead, QCCJ) | 84-pin PLCC (J-lead) |
| Mounting Type | Surface Mount (PLCC socket compatible) | Surface Mount (PLCC socket or direct solder) |
| Programming Interface | JTAG (IEEE 1149.1) / ISP | β |
| Pin Count | 84 | β |
| RoHS Status | Non-compliant (legacy 5V part, SnPb finish) | [DATA_NEEDED: RoHS status - not stated in verified data] |
| Product Type | β | CPLD (Complex Programmable Logic Device) |
| Logic Elements / Gates | β | 2500 usable gates |
| User I/O Pins | β | 68 |
| Number of Logic Array Blocks (LABs) | β | 8 |
| Propagation Delay (tPD) | β | 10 ns |
| Setup Time (tSU) | β | 7 ns |
| Maximum Operating Frequency | β | 125 MHz (counter) |
| Supply Voltage (VCCINT) | β | 4.75 V to 5.25 V (5 V nominal) |
| I/O Voltage (MultiVolt) | β | 2.5 V / 3.3 V / 5.0 V |
| Program Memory Type | β | EEPROM (in-system programmable) |
| JTAG Support | β | IEEE Std 1149.1 boundary-scan |