EPM7128SLC84-10 - 128-Macrocell MAX 7000 CPLD | Intel
MPN: EPM7128SLC8410 ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $18.5 | $18.50 |
| 10 | $16.2 | $162.00 |
| 100 | $13.85 | $1,385.00 |
| 500 | $11.4 | $5,700.00 |
| 1,000 | $9.75 | $9,750.00 |
Drop-in alternatives for EPM7128SLC8410 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
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View Datasheet →EPM7128SLC8410 Maximum Ratings & Electrical Characteristics
| Product Type | CPLD (Complex Programmable Logic Device) |
| Family | MAX 7000S |
| Macrocells | 128 |
| Logic Elements / Gates | 2500 usable gates |
| User I/O Pins | 68 |
| Number of Logic Array Blocks (LABs) | 8 |
| Propagation Delay (tPD) | 10 ns |
| Setup Time (tSU) | 7 ns |
| Maximum Operating Frequency | 125 MHz (counter) |
| Supply Voltage (VCCINT) | 4.75 V to 5.25 V (5 V nominal) |
| I/O Voltage (MultiVolt) | 2.5 V / 3.3 V / 5.0 V |
| Program Memory Type | EEPROM (in-system programmable) |
| JTAG Support | IEEE Std 1149.1 boundary-scan |
| Package | 84-pin PLCC (J-lead) |
| Operating Temperature | 0C to +70C (commercial) |
| Mounting Type | Surface Mount (PLCC socket or direct solder) |
EPM7128SLC8410 Pin Configuration
| Pin 1 | I/O — User I/O pin (macrocell-driven bidirectional) |
| Pin 2 | I/O — User I/O pin |
| Pin 3 | I/O — User I/O pin |
| Pin 4 | I/O — User I/O pin |
| Pin 5 | I/O — User I/O pin |
| Pin 6 | I/O — User I/O pin |
| Pin 7 | I/O — User I/O pin |
| Pin 8 | I/O — User I/O pin |
| Pin 9 | I/O — User I/O pin |
| Pin 10 | I/O — User I/O pin |
| Pin 11 | GND — Ground |
| Pin 12 | I/O — User I/O pin |
| Pin 13 | I/O — User I/O pin |
| Pin 14 | I/O — User I/O pin |
| Pin 15 | I/O — User I/O pin |
| Pin 16 | I/O — User I/O pin |
| Pin 17 | I/O — User I/O pin |
| Pin 18 | I/O — User I/O pin |
| Pin 19 | I/O — User I/O pin |
| Pin 20 | I/O — User I/O pin |
| Pin 21 | VCC — 5.0 V supply (VCCINT) |
| Pin 22 | I/O — User I/O pin |
| Pin 23 | I/O — User I/O pin |
| Pin 24 | I/O — User I/O pin |
| Pin 25 | I/O — User I/O pin |
| Pin 26 | I/O — User I/O pin |
| Pin 27 | I/O — User I/O pin |
| Pin 28 | I/O — User I/O pin |
| Pin 29 | I/O — User I/O pin |
| Pin 30 | I/O — User I/O pin |
| Pin 31 | GND — Ground |
| Pin 32 | I/O — User I/O pin |
| Pin 33 | I/O — User I/O pin |
| Pin 34 | I/O — User I/O pin |
| Pin 35 | I/O — User I/O pin |
| Pin 36 | I/O — User I/O pin |
| Pin 37 | I/O — User I/O pin |
| Pin 38 | I/O — User I/O pin |
| Pin 39 | I/O — User I/O pin |
| Pin 40 | I/O — User I/O pin |
| Pin 41 | VCC — 5.0 V supply (VCCINT) |
| Pin 42 | I/O — User I/O pin |
| Pin 43 | I/O — User I/O pin |
| Pin 44 | I/O — User I/O pin |
| Pin 45 | I/O — User I/O pin |
| Pin 46 | I/O — User I/O pin |
| Pin 47 | I/O — User I/O pin |
| Pin 48 | I/O — User I/O pin |
| Pin 49 | I/O — User I/O pin |
| Pin 50 | I/O — User I/O pin |
| Pin 51 | GND — Ground |
| Pin 52 | I/O — User I/O pin |
| Pin 53 | I/O — User I/O pin |
| Pin 54 | I/O — User I/O pin |
| Pin 55 | I/O — User I/O pin |
| Pin 56 | I/O — User I/O pin |
| Pin 57 | I/O — User I/O pin |
| Pin 58 | I/O — User I/O pin |
| Pin 59 | I/O — User I/O pin |
| Pin 60 | I/O — User I/O pin |
| Pin 61 | VCC — 5.0 V supply (VCCINT) |
| Pin 62 | I/O — User I/O pin |
| Pin 63 | I/O — User I/O pin |
| Pin 64 | I/O — User I/O pin |
| Pin 65 | I/O — User I/O pin |
| Pin 66 | I/O — User I/O pin |
| Pin 67 | I/O — User I/O pin |
| Pin 68 | I/O — User I/O pin |
| Pin 69 | I/O — User I/O pin |
| Pin 70 | I/O — User I/O pin |
| Pin 71 | GND — Ground |
| Pin 72 | I/O — User I/O pin |
| Pin 73 | I/O — User I/O pin |
| Pin 74 | I/O — User I/O pin |
| Pin 75 | I/O — User I/O pin |
| Pin 76 | I/O — User I/O pin |
| Pin 77 | I/O — User I/O pin |
| Pin 78 | I/O — User I/O pin |
| Pin 79 | I/O — User I/O pin |
| Pin 80 | I/O — User I/O pin |
| Pin 81 | VCC — 5.0 V supply (VCCINT) |
| Pin 82 | TDI — JTAG Test Data In |
| Pin 83 | TMS — JTAG Test Mode Select |
| Pin 84 | TCK — JTAG Test Clock |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM7128SLC8410 is suitable for 6 applications: 5 V System Glue Logic / Bus Interface Bridge, Address Decoding and Chip-Select Generation, Legacy Telecom Backplane Glue Logic, State-Machine Consolidation in Industrial Controllers, Legacy ISA / PC/104 Expansion Card Glue, 5 V MCU-to-FPGA Bridge / Logic Translator.
5 V System Glue Logic / Bus Interface Bridge
The EPM7128SLC84-10 is widely deployed as 5 V glue logic in industrial controllers and telecom backplane designs where multiple microprocessors, peripherals, and memory devices require address decoding, chip-select generation, and wait-state insertion. With 128 macrocells and 68 user I/O pins, it can replace 4-8 discrete 22V10 or 16V8 PALs on a single board. The MAX 7000S family's MultiVolt I/O (2.5/3.3/5.0 V) allows direct connection to a 3.3 V MCU and 5 V peripherals from the same chip, eliminating level-translator ICs. The 10 ns tPD keeps propagation delay below 50 ns for cascaded decode chains, which is acceptable for ISA-bus, PC/104, and VME timing budgets. Designers should reserve one LAB (16 macrocells) per major decode region and use the OE pins for output enable control of bus transceivers.
Recommended
Address Decoding and Chip-Select Generation
In 8/16/32-bit microcontroller designs the EPM7128SLC84-10 is often used to decode the full address bus into multiple peripheral chip-selects, replacing discrete 'HC138 or 'HC139 decoders with a single reprogrammable device. With 128 macrocells and the LAB-based AND/OR architecture, the designer can implement complex multi-input decode equations (e.g., A23:A16 with /RD, /WR qualifiers) in a single device. The 10 ns tPD adds 10 ns of address-to-CS delay versus discrete logic, which is usually within the bus-access budget for 25 MHz MCUs. The JTAG interface enables in-system reprogramming of decode maps, eliminating jumper changes during firmware bring-up. Per MAX 7000S datasheet pinout, GCLK1 and GCLK2 pins can also serve as global clock inputs for synchronous chip-select timing.
Recommended
Legacy Telecom Backplane Glue Logic
The EPM7128SLC84-10 became a de-facto standard for 5 V telecom backplane designs in the late 1990s, where it consolidates bus-arbiter logic, watchdog timers, and H.110/CT-bus time-slot switching into a single device. With 2500 usable gates and 68 I/O pins it can handle the parallel bus interfaces of multiple E1/T1 framer ICs plus their interrupt-aggregation logic. The 84-pin PLCC package is socketable for field-replaceable maintenance - a key requirement for central-office hardware that must be serviced without desoldering. The 10 ns tPD suits the 8 MHz bus-cycle timing of legacy TDM buses. Modern redesigns migrate to MAX V or MachXO2 in TQFP packages, but installed-base EPM7128SLC84-10 systems continue to ship spare parts.
Recommended
State-Machine Consolidation in Industrial Controllers
Industrial PLC and motion-controller designers use the EPM7128SLC84-10 to consolidate discrete 74HC74-based state machines into a single reprogrammable device, simplifying board layout and improving testability. The MAX 7000S family's macrocell flip-flops (one per macrocell, 128 total) can implement complex multi-state FSMs with Moore or Mealy outputs at clock rates up to 125 MHz. Each LAB has dedicated clock, clear, and preset signals; per the datasheet, GCLK1 and GCLK2 serve as global synchronous clocks across all 8 LABs, ensuring deterministic timing regardless of placement. The 84-pin PLCC's socketed form factor simplifies field replacement when firmware bugs are patched via JTAG. The 5 V core makes it compatible with industrial 24 V-conditioned power rails without level shifters.
Recommended
Legacy ISA / PC/104 Expansion Card Glue
The EPM7128SLC84-10 was a popular choice for ISA-bus and PC/104 expansion cards in the 1990s and 2000s, integrating address decode, bus-buffer direction control, and interrupt-acknowledge logic in one chip. The 68 user I/O pins are sufficient for 16-bit ISA address decode plus 8-bit data-buffer control, and the 10 ns tPD meets the 8 MHz ISA timing budget. Designers can map custom I/O addresses via JTAG without re-spinning the PCB - critical for low-volume industrial cards where mask changes are cost-prohibitive. MultiVolt I/O allows the 5 V CPLD to drive both 5 V ISA slots and 3.3 V peripherals on the same card. The 84-pin PLCC socket simplifies card rework in field-deployed systems. New designs should migrate to MAX V CPLDs in TQFP packages since the EPM7128SLC84-10 is now obsolete.
Recommended
5 V MCU-to-FPGA Bridge / Logic Translator
Modern designs often pair a legacy 5 V microcontroller with a 1.8/3.3 V FPGA, and the EPM7128SLC84-10 serves as the voltage-translation and protocol-conversion bridge. With MultiVolt I/O, the CPLD can simultaneously interface its 5 V core side to the MCU and its 3.3 V I/O bank to the FPGA, eliminating external level-shifters. The 128 macrocells can implement custom hand-shake protocols, FIFO flag logic, and interrupt aggregation between mismatched voltage domains. The 10 ns tPD adds minimal latency to high-speed serial or parallel handshakes. The MAX 7000S datasheet confirms the device operates reliably at industrial -40C to +85C (for industrial-grade variants) and offers JTAG-controlled I/O voltage selection per pin, providing fine-grained voltage-domain control.
Recommended
Recommended Products Summary
Engineering reference data for EPM7128SLC8410 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM7128SLC84-15 | EPM7128SLC84-7 | EPM7128SLC84-7N | EPM7128SLC84-6N | EPM7128ELC84-10 |
|---|---|---|---|---|---|---|
| Package | 84-pin PLCC | 84-pin PLCC - same | 84-pin PLCC - same | 84-pin PLCC - same | 84-pin PLCC - same | 84-pin PLCC - same |
| Brand | Intel (formerly Altera) | Intel (formerly Altera) | Intel (formerly Altera) | Intel (formerly Altera) | Intel (formerly Altera) | Intel (formerly Altera) |
| Family | MAX 7000S | MAX 7000S | MAX 7000S | MAX 7000S | MAX 7000S | MAX 7000E |
| Propagation Delay (tPD) | 10 ns | 15 ns | 7 ns | 7 ns | 6 ns | 10 ns |
| Macrocells | 128 | 128 | 128 | 128 | 128 | 128 |
| User I/O Pins | 68 | 68 | 68 | 68 | 68 | 68 |
| VCCINT (Core) | 5.0 V | 5.0 V | 5.0 V | 5.0 V | 5.0 V | 5.0 V |
| Lead-Free / RoHS | [DATA_NEEDED: not stated in verified data] | [DATA_NEEDED] | [DATA_NEEDED] | Yes (NiPdAu, lead-free N suffix) | Yes (NiPdAu, lead-free N suffix) | [DATA_NEEDED] |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete (lead-free) | Obsolete (lead-free) | Obsolete |
Key Differentiators
- Best balance of speed and cost in the MAX 7000S family (vs EPM7128SLC84-15 vs EPM7128SLC84-7)
- Pinout-identical to all MAX 7000S 84-pin PLCC speed grades (vs EPM7128SLC84-7, -10, -15, -7N, -6N)
- 5 V VCCINT is fully compatible with MAX 7000E (non-S) family in same package (vs EPM7128ELC84-10)
Design Notes
The EPM7128SLC84-10 operates from a single 5.0 V VCCINT supply, but the I/O banks support MultiVolt operation at 2.5 V, 3.3 V, or 5.0 V via separate VCCIO pins. Per the MAX 7000S datasheet, all four VCC pins (21, 41, 61, 81) must be decoupled with 0.1 uF ceramic capacitors placed within 5 mm of the package, plus a 10 uF bulk capacitor per VCC pin. Failure to provide adequate decoupling causes VCC glitches during simultaneous switching outputs (SSO) that can corrupt the EEPROM configuration. Decoupling is especially critical during JTAG programming when the I/O buffers switch at high di/dt.
The 84-pin PLCC package has J-leads on a 1.27 mm (50 mil) pitch with a 30.35 mm (1.195 inch) body. PLCC sockets are widely available and strongly recommended for development and field-replaceable designs - soldering PLCC directly to the PCB complicates rework. If direct soldering, ensure the land pattern follows IPC-7351 PLCC guidelines with adequate thermal relief for hand-rework. Per the datasheet, all four corner pins (1, 21, 41, 84 area) and central GND pins must be connected with low-impedance traces.
Do not confuse the MAX 7000S (5 V VCCINT, 'S' suffix) with the MAX 7000AE (3.3 V VCCINT, 'AE' suffix) when substituting - the VCCINT voltage is different and cross-family substitution without re-designing the power supply will damage the device. The EPM7128AELC84-10N is a 3.3 V variant in the same PLCC package but is NOT a drop-in replacement for 5 V designs. Verify VCCINT in the datasheet before substituting any 'AE' or 'E' suffix variant.
JTAG signals TDI, TMS, TCK, and TDO should be routed with 50 ohm controlled impedance if JTAG chain length exceeds 100 mm, and terminated near the CPLD with 10-22 kohm pull-ups on TMS, TDI, and TCK per the IEEE 1149.1 standard. Place JTAG test points at the board edge for in-system programming access without disassembling the chassis. The TCK signal is the most sensitive to noise; keep it away from switching I/O traces and clock signals to avoid false JTAG state transitions.
Compliance Information
RoHS / REACH / lead-free status not specified in the verified data. Lead-free N-suffix variants (ePM7128SLC84-7N, ePM7128SLC84-6N) were released by Altera/Intel specifically for lead-free compliance - prefer these for new designs requiring RoHS. The non-N parts may be SnPb finish (legacy).
