EPM7128EQC100-20 vs EPM7128EQI100-15 Comparison
Detailed side-by-side comparison of EPM7128EQC100-20 by Altera and EPM7128EQI100-15 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM7128EQI100-15 - MAX 7000 CPLD, 128 Macrocells, 15ns | Altera/Intel
EPM7128EQI100-15 ObsoleteSpecification Comparison
| Parameter | EPM7128EQC100-20 | EPM7128EQI100-15 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | NRND | Obsolete |
| Family | MAX 7000 | MAX 7000 |
| Device Type | EPLD (Complex Programmable Logic Device) | CPLD - Complex Programmable Logic Device |
| Macrocells | 128 | 128 |
| Usable Gates | 2.5K | 2.5K |
| User I/Os | 84 | — |
| Logic Elements / LABs | 8 LABs (16 macrocells per LAB) | — |
| Propagation Delay (tpd) | 20 ns | — |
| Maximum Internal Frequency | 250 MHz | — |
| Technology | CMOS, UV-erasable / EEPROM | — |
| Supply Voltage | 5 V | — |
| Operating Temperature | 0 C to 90 C (Commercial) | -40 °C to +85 °C (industrial grade, "I" suffix) |
| Package | 100-pin PQFP (BQFP, gull-wing) | 100-pin PQFP (BQFP, 14x20 mm) |
| Mounting Type | Surface Mount | Surface Mount |
| In-System Programming | Yes (IEEE 1149.1 JTAG) | — |
| Compliance | RoHS compliance status not confirmed in web data | — |
| Logic Array Blocks (LABs) | — | 8 (16 macrocells each) |
| User I/O Pins | — | 84 |
| Pin-to-Pin Propagation Delay (tPD) | — | 15 ns |
| Maximum Operating Frequency | — | 76.9 MHz |
| Supply Voltage (VCCINT/VCCIO) | — | 4.75 V to 5.25 V (5 V nominal) |
| Programming Technology | — | EEPROM (non-volatile, in-system programmable) |
| Boundary Scan | — | IEEE 1149.1 (JTAG) compliant |
| RoHS Status | — | Compliant (lead-free; verify per lot) |
| Manufacturer | — | Altera (now Intel FPGA) |