EPM7128EQC100-20 vs EPM7128EQI100-15 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM7128EQC100-20 sa pamamagitan ng Altera at EPM7128EQI100-15 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Altera
EPM7128EQI100-15 - MAX 7000 CPLD, 128 Macrocells, 15ns | Altera/Intel
EPM7128EQI100-15 ObsoletePagsanggunian na paghahambing
| Parametro | EPM7128EQC100-20 | EPM7128EQI100-15 |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | NRND | Obsolete |
| Family | MAX 7000 | MAX 7000 |
| Device Type | EPLD (Complex Programmable Logic Device) | CPLD - Complex Programmable Logic Device |
| Macrocells | 128 | 128 |
| Usable Gates | 2.5K | 2.5K |
| User I/Os | 84 | — |
| Logic Elements / LABs | 8 LABs (16 macrocells per LAB) | — |
| Propagation Delay (tpd) | 20 ns | — |
| Maximum Internal Frequency | 250 MHz | — |
| Technology | CMOS, UV-erasable / EEPROM | — |
| Volte ng Pagbibigay | 5 V | — |
| Temperature na Operasyon | 0 C to 90 C (Commercial) | -40 °C to +85 °C (industrial grade, "I" suffix) |
| Packhaging | 100-pin PQFP (BQFP, gull-wing) | 100-pin PQFP (BQFP, 14x20 mm) |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| In-System Programming | Yes (IEEE 1149.1 JTAG) | — |
| Compliance | RoHS compliance status not confirmed in web data | — |
| Logic Array Blocks (LABs) | — | 8 (16 macrocells each) |
| User I/O Pins | — | 84 |
| Pin-to-Pin Propagation Delay (tPD) | — | 15 ns |
| Maximum Operating Frequency | — | 76.9 MHz |
| Supply Voltage (VCCINT/VCCIO) | — | 4.75 V to 5.25 V (5 V nominal) |
| Programming Technology | — | EEPROM (non-volatile, in-system programmable) |
| Boundary Scan | — | IEEE 1149.1 (JTAG) compliant |
| Tindminan RoHS | — | Compliant (lead-free; verify per lot) |
| Manufacturer | — | Altera (now Intel FPGA) |