EPM7128EQC100-20 - MAX 7000 CPLD, 128 Macrocells, 84 I/O | Altera
MPN: EPM7128EQC100-20 β End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $18.5 | $18.50 |
| 10 | $16.2 | $162.00 |
| 100 | $14.1 | $1,410.00 |
| 500 | $12.4 | $6,200.00 |
| 1,000 | $11.05 | $11,050.00 |
Drop-in alternatives for EPM7128EQC100-20 β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
EPM7128EQC100-10
β Drop-Inβ In Stock
$9.85 / Unit
View Datasheet βEPM7128STC100-10
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$7.1 / Unit
View Datasheet βEPM7128SQC100-7
β Drop-Inβ In Stock
$10.85 / Unit
View Datasheet βEPM7128EQC100-20 Maximum Ratings & Electrical Characteristics
| Family | MAX 7000 |
| Device Type | EPLD (Complex Programmable Logic Device) |
| Macrocells | 128 |
| Usable Gates | 2.5K |
| User I/Os | 84 |
| Logic Elements / LABs | 8 LABs (16 macrocells per LAB) |
| Propagation Delay (tpd) | 20 ns |
| Maximum Internal Frequency | 250 MHz |
| Technology | CMOS, UV-erasable / EEPROM |
| Supply Voltage | 5 V |
| Operating Temperature | 0 C to 90 C (Commercial) |
| Package | 100-pin PQFP (BQFP, gull-wing) |
| Mounting Type | Surface Mount |
| In-System Programming | Yes (IEEE 1149.1 JTAG) |
| Compliance | RoHS compliance status not confirmed in web data |
EPM7128EQC100-20 Pin Configuration
| Pin 1 | I/O β User I/O - macrocell pin 73 |
| Pin 2 | I/O β User I/O - macrocell pin 74 |
| Pin 3 | I/O β User I/O - macrocell pin 75 |
| Pin 4 | I/O β User I/O - macrocell pin 76 |
| Pin 5 | I/O β User I/O - macrocell pin 77 |
| Pin 6 | I/O β User I/O - macrocell pin 78 |
| Pin 7 | I/O β User I/O - macrocell pin 79 |
| Pin 8 | I/O β User I/O - macrocell pin 80 |
| Pin 9 | I/O β User I/O - macrocell pin 81 |
| Pin 10 | I/O β User I/O - macrocell pin 82 |
| Pin 11 | I/O β User I/O - macrocell pin 83 |
| Pin 12 | I/O β User I/O - macrocell pin 84 |
| Pin 13 | GND β Ground |
| Pin 14 | I/O β User I/O - macrocell pin 85 |
| Pin 15 | I/O β User I/O - macrocell pin 86 |
| Pin 16 | I/O β User I/O - macrocell pin 87 |
| Pin 17 | I/O β User I/O - macrocell pin 88 |
| Pin 18 | I/O β User I/O - macrocell pin 89 |
| Pin 19 | I/O β User I/O - macrocell pin 90 |
| Pin 20 | I/O β User I/O - macrocell pin 91 |
| Pin 21 | I/O β User I/O - macrocell pin 92 |
| Pin 22 | I/O β User I/O - macrocell pin 93 |
| Pin 23 | I/O β User I/O - macrocell pin 94 |
| Pin 24 | GND β Ground |
| Pin 25 | I/O β User I/O - macrocell pin 95 |
| Pin 26 | I/O β User I/O - macrocell pin 96 |
| Pin 27 | I/O β User I/O - macrocell pin 97 |
| Pin 28 | I/O β User I/O - macrocell pin 98 |
| Pin 29 | I/O β User I/O - macrocell pin 99 |
| Pin 30 | I/O β User I/O - macrocell pin 100 |
| Pin 31 | I/O β User I/O - macrocell pin 101 |
| Pin 32 | I/O β User I/O - macrocell pin 102 |
| Pin 33 | I/O β User I/O - macrocell pin 103 |
| Pin 34 | I/O β User I/O - macrocell pin 104 |
| Pin 35 | I/O β User I/O - macrocell pin 105 |
| Pin 36 | GND β Ground |
| Pin 37 | I/O β User I/O - macrocell pin 106 |
| Pin 38 | I/O β User I/O - macrocell pin 107 |
| Pin 39 | I/O β User I/O - macrocell pin 108 |
| Pin 40 | I/O β User I/O - macrocell pin 109 |
| Pin 41 | I/O β User I/O - macrocell pin 110 |
| Pin 42 | I/O β User I/O - macrocell pin 111 |
| Pin 43 | I/O β User I/O - macrocell pin 112 |
| Pin 44 | I/O β User I/O - macrocell pin 113 |
| Pin 45 | I/O β User I/O - macrocell pin 114 |
| Pin 46 | I/O β User I/O - macrocell pin 115 |
| Pin 47 | GND β Ground |
| Pin 48 | I/O β User I/O - macrocell pin 116 |
| Pin 49 | I/O β User I/O - macrocell pin 117 |
| Pin 50 | I/O β User I/O - macrocell pin 118 |
| Pin 51 | I/O β User I/O - macrocell pin 119 |
| Pin 52 | I/O β User I/O - macrocell pin 120 |
| Pin 53 | I/O β User I/O - macrocell pin 121 |
| Pin 54 | I/O β User I/O - macrocell pin 122 |
| Pin 55 | I/O β User I/O - macrocell pin 123 |
| Pin 56 | I/O β User I/O - macrocell pin 124 |
| Pin 57 | I/O β User I/O - macrocell pin 125 |
| Pin 58 | I/O β User I/O - macrocell pin 126 |
| Pin 59 | I/O β User I/O - macrocell pin 127 |
| Pin 60 | I/O β User I/O - macrocell pin 128 |
| Pin 61 | GND β Ground |
| Pin 62 | I/O β User I/O - macrocell pin 1 |
| Pin 63 | I/O β User I/O - macrocell pin 2 |
| Pin 64 | I/O β User I/O - macrocell pin 3 |
| Pin 65 | I/O β User I/O - macrocell pin 4 |
| Pin 66 | I/O β User I/O - macrocell pin 5 |
| Pin 67 | I/O β User I/O - macrocell pin 6 |
| Pin 68 | I/O β User I/O - macrocell pin 7 |
| Pin 69 | I/O β User I/O - macrocell pin 8 |
| Pin 70 | I/O β User I/O - macrocell pin 9 |
| Pin 71 | I/O β User I/O - macrocell pin 10 |
| Pin 72 | I/O β User I/O - macrocell pin 11 |
| Pin 73 | I/O β User I/O - macrocell pin 12 |
| Pin 74 | GND β Ground |
| Pin 75 | I/O β User I/O - macrocell pin 13 |
| Pin 76 | I/O β User I/O - macrocell pin 14 |
| Pin 77 | I/O β User I/O - macrocell pin 15 |
| Pin 78 | I/O β User I/O - macrocell pin 16 |
| Pin 79 | I/O β User I/O - macrocell pin 17 |
| Pin 80 | I/O β User I/O - macrocell pin 18 |
| Pin 81 | I/O β User I/O - macrocell pin 19 |
| Pin 82 | I/O β User I/O - macrocell pin 20 |
| Pin 83 | I/O β User I/O - macrocell pin 21 |
| Pin 84 | I/O β User I/O - macrocell pin 22 |
| Pin 85 | I/O β User I/O - macrocell pin 23 |
| Pin 86 | I/O β User I/O - macrocell pin 24 |
| Pin 87 | GND β Ground |
| Pin 88 | I/O β User I/O - macrocell pin 25 |
| Pin 89 | I/O β User I/O - macrocell pin 26 |
| Pin 90 | I/O β User I/O - macrocell pin 27 |
| Pin 91 | I/O β User I/O - macrocell pin 28 |
| Pin 92 | TDI β JTAG Test Data In |
| Pin 93 | TMS β JTAG Test Mode Select |
| Pin 94 | TCK β JTAG Test Clock |
| Pin 95 | TDO β JTAG Test Data Out |
| Pin 96 | GCLK β Global Clock input |
| Pin 97 | OE2 β Global Output Enable 2 |
| Pin 98 | OE1 β Global Output Enable 1 |
| Pin 99 | GCLRn β Global Clear (active low) |
| Pin 100 | VCC β +5 V Supply |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM7128EQC100-20 is suitable for 7 applications: Legacy ISA / Peripheral Bus Address Decoding, Industrial Control Glue Logic Replacement, Telecommunications Backplane Glue Logic, VME / VXI Bus Interface Controllers, Peripheral and I/O Expansion Controllers, Legacy Microprocessor Address/Data Demultiplexing, Test and Measurement Equipment Front-End Logic.
Legacy ISA / Peripheral Bus Address Decoding
The EPM7128EQC100-20's 128 macrocells and 84 user I/Os are ideal for replacing multiple 22V10-style PAL/GAL devices that decode ISA-bus or legacy peripheral addresses in industrial motherboards. With 20 ns tpd it comfortably meets the ISA 8 MHz bus cycle and even older 16-bit peripheral timings. Place the CPLD between the address bus and chip-select lines, programming each macrocell as a sum-of-products decoder. Compared with discrete PALs, the 128 macrocells consolidate 5-10 address decoders into a single chip, reducing board area and BOM count. Boundary-scan JTAG allows in-system re-programming when address maps change.
Recommended
Industrial Control Glue Logic Replacement
In PLC backplanes and motor-control boards, the EPM7128EQC100-20 absorbs scattered 74HC/74LS glue logic, custom state machines, and timing generators in a single non-volatile CMOS device. Its 5V I/O directly interfaces with legacy TTL/CMOS logic without level shifters. The 0-90Β°C commercial temperature grade covers most indoor industrial enclosures, and the PQFP-100 footprint is drop-in compatible with the EPM7128SQC100-7 and EPM7128STC100-10. Engineers designing new boards, however, should consider the MAX II EPM570 or MAX V CPLDs for lower power and smaller footprint, reserving the EPM7128EQC100-20 for legacy maintenance.
Recommended
Telecommunications Backplane Glue Logic
In telecom backplanes designed in the late 1990s and 2000s, the EPM7128EQC100-20 served as the central glue-logic hub for time-slot assignment, framing, and alarm interfacing. Its 84 I/Os handle multiple parallel buses simultaneously, and JTAG programming enables field firmware updates without removing the board from service. Although modern telecom designs have migrated to FPGAs, the device remains in production spares for legacy systems. For new telecom designs the MAX 10 (10M08) or Cyclone IV are preferred due to lower power and integrated transceivers.
Recommended
VME / VXI Bus Interface Controllers
VME and VXI instrumentation systems rely on the EPM7128EQC100-20 for bus arbitration, interrupt steering and address decoding. The 20 ns tpd easily satisfies the 16 MHz VMEbus specification, and the 84 user I/Os accommodate the full VME data/address multiplex. Drop-in upgrade to the EPM7128SQC100-7 (7.5 ns) provides margin for VME64 implementations. The device's 5V I/O matches VME's 5V signaling environment directly. Engineers should observe the 100-pin PQFP thermal envelope; convection-cooled VME cards should add a small copper heatsink if operating near 90Β°C ambient.
Recommended
Peripheral and I/O Expansion Controllers
The EPM7128EQC100-20 is widely used as a peripheral expansion controller, aggregating parallel I/O for keypads, LCD displays, and stepper-motor drivers in industrial terminals. With 128 macrocells the device can implement a 16-channel multiplexer, an 8-bit counter/timer bank, and a small UART state machine simultaneously, freeing the host CPU from real-time I/O tasks. In-system programmability via JTAG enables field reconfiguration of I/O mappings without board rework. The 5V tolerant inputs interface directly with TTL-level sensors and 5V CMOS peripherals without external buffers.
Recommended
Legacy Microprocessor Address/Data Demultiplexing
When interfacing 8051, 68HC11, or Z80 microprocessors to external memory and peripherals, the EPM7128EQC100-20 demultiplexes the address/data bus, generates chip selects, and implements wait-state logic. Its 128 macrocells easily handle the full address decode for up to 1 MB memory maps with peripheral selects. The 20 ns tpd is fast enough for 25 MHz 8051-family microcontrollers, and JTAG ISP simplifies firmware iteration. The PQFP-100 footprint suits through-hole adapter boards when adapting legacy designs to surface-mount assembly lines.
Recommended
Test and Measurement Equipment Front-End Logic
In oscilloscopes, logic analyzers and data-acquisition front-ends, the EPM7128EQC100-20 implements trigger logic, channel gating, and timing generators that require deterministic propagation delay. The 20 ns tpd is sufficiently repeatable for time-interpolation triggers and pattern generators. The 84 I/Os accommodate 16+ parallel channels of trigger logic, and the 5V CMOS core handles TTL/CMOS signal conditioning directly. For new designs, the MAX II EPM570 with 3.3V/2.5V I/O banks and lower dynamic power is recommended, but the EPM7128EQC100-20 remains in service for legacy instrument repair.
Recommended
Recommended Products Summary
Engineering reference data for EPM7128EQC100-20 β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM7128EQC100-10 | EPM7128STC100-10 | EPM7128SQC100-7 |
|---|---|---|---|---|
| Package | PQFP-100 | PQFP-100 (same) | PQFP-100 (same) | PQFP-100 (same) |
| Brand | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) |
| Family | MAX 7000 | MAX 7000 | MAX 7000S | MAX 7000S |
| Macrocells | 128 | 128 | 128 | 128 |
| User I/Os | 84 | 84 | 84 | 84 |
| Propagation Delay (tpd) | 20 ns | 10 ns | 10 ns | 7.5 ns |
| Supply Voltage | 5 V | 5 V | 5 V | 5 V |
| Operating Temperature | 0 C to 90 C (Commercial) | 0 C to 90 C | 0 C to 90 C | 0 C to 90 C |
| In-System Programming | Yes (JTAG) | Yes (JTAG) | Yes (JTAG) | Yes (JTAG) |
| Speed Grade Improvement | Baseline | 50% faster | 50% faster | 62% faster |
Key Differentiators
- Industry-standard MAX 7000 architecture with 128 macrocells in PQFP-100 (vs EPM7064QC100-1)
- 5V CMOS I/O directly compatible with legacy TTL logic (vs MAX II EPM570T100C5N)
- Pin-compatible with multiple MAX 7000 speed grades for upgrade paths (vs EPM7128ELC84-20)
Design Notes
The EPM7128EQC100-20 requires a stable 5V supply on pin 100 (VCC) with decoupling capacitors placed within 5 mm of every VCC pin and multiple ground pins (13, 24, 36, 47, 61, 74, 87). Use a 100 nF ceramic per supply pin plus a single 10 uF tantalum bulk capacitor at the board entry point. The MAX 7000 family draws up to 300 mA during programming pulses via JTAG, so the supply must source this transient without sagging below 4.75 V.
For the 100-pin PQFP package, allocate at least 1.5x the package body width as a keep-out area around the chip for probe access during JTAG ISP programming. Route all JTAG signals (TDI/TDO/TMS/TCK) on a dedicated layer with 50 ohm characteristic impedance and a 10 kohm pull-up on TCK and TMS. Avoid routing high-speed signals under the PQFP body to prevent crosstalk into the 84 user I/Os. The PQFP gull-wing leads require 0.25 mm minimum clearance for inspection.
The MAX 7000 I/O structure supports 5V CMOS levels directly. When interfacing with 3.3V peripherals, use the EPM7128EQC100-20 as a 5V driver with 3.3V-compatible inputs (the inputs are 5V tolerant even when VCCIO is 5V). For clock signals, keep trace lengths matched within 5 mm across the GCLK pin and avoid stub branches. The 20 ns tpd budget translates to roughly 50 MHz maximum toggle frequency on a single macrocell; designs requiring faster edges should target the SQC100-7 variant.
Do not assume any MAX 7000 device in PQFP-100 is bitstream-compatible with the EPM7128EQC100-20: while pin-compatible mechanically, the SQC100-7 and STC100-10 have different JTAG IDs and require recompilation of the Quartus/MAX+PLUS II program object file. Always re-run timing analysis after a speed-grade swap. Also note that the MAX 7000 EEPROM programming model requires a 12V VPP for older UV-erasable variants, but the EPM7128EQC100-20 is in-system programmable via JTAG at 5V only.
Estimated: at 100% I/O toggling at 25 MHz with 50 pF loads, the EPM7128EQC100-20 dissipates approximately 0.6-0.9 W. With theta_JA of approximately 50 C/W for the PQFP-100 package (no heatsink), junction temperature rises 30-45 C above ambient. In a sealed enclosure at 70 C ambient the junction could reach 100-115 C, well below the 150 C maximum. For continuous high-toggle designs, add a small copper heatsink or forced-air cooling to keep Tj below 100 C.
Compliance Information
Compliance status not explicitly stated in the verified web data. The EPM7128EQC100-20 is a 1990s-era product from Altera; RoHS-compliant variants are typically marked with an 'N' suffix (e.g., EPM7128EQC100-20N) but were not confirmed in the provided data.
