EPM7128SLC84-10 vs EPM7096LC84-15 Comparison
Detailed side-by-side comparison of EPM7128SLC84-10 by Intel and EPM7096LC84-15 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM7128SLC84-10 | EPM7096LC84-15 |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Family | MAX 7000S | MAX 7000 |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Macrocells | 128 | — |
| Logic Gates | 2500 | — |
| User I/Os | 68 | — |
| Total Package Pins | 84 | — |
| Package | PLCC-84 (J-lead) | — |
| Propagation Delay (tpd) | 10 ns | — |
| Maximum Operating Frequency | 125 MHz | 76.9 MHz |
| Internal Frequency | 250 MHz | — |
| Supply Voltage (VCCINT) | 5 V | — |
| MultiVolt I/O Support | 2.5 V / 3.3 V / 5 V | — |
| Program Memory Type | EEPROM (in-system programmable) | — |
| JTAG (IEEE 1149.1) | Yes | — |
| Operating Temperature | 0C to +70C (Commercial) | 0C to +70C (commercial) |
| Mounting Type | Surface Mount (J-bend) | Surface Mount |
| MSL Level | [DATA_NEEDED: MSL level] | — |
| RoHS Status | Non-compliant (contains lead in PLCC) | [DATA_NEEDED: RoHS compliance status] |
| Series | — | MAX 7000 (second-generation MAX architecture) |
| Macro Cells | — | 96 |
| Logic Array Blocks (LABs) | — | 4 |
| Usable Gates | — | 1,800 |
| Pin-to-Pin Propagation Delay (tPD) | — | 15 ns |
| User I/O Pins | — | 68 (36 per LAB, [DATA_NEEDED: exact LAB-level split]) |
| Supply Voltage (VCC) | — | 4.75 V to 5.25 V |
| Programmable Type | — | EE PLD (in-system programmable via JTAG) |
| Programming Interface | — | IEEE Std. 1149.1 JTAG |
| Package / Case | — | 84-PLCC (J-Lead) |
| Supplier Device Package | — | 84-PLCC (29.31 x 29.31 mm) |
| Data Retention | — | [DATA_NEEDED: data retention years] |
| Erase/Program Endurance | — | [DATA_NEEDED: erase/program cycle count] |