EPM7096LC84-15 - 96 Macrocell, 15ns CPLD MAX 7000 | Intel / Altera
MPN: EPM7096LC84-15 β End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $18.5 | $18.50 |
| 10 | $16.2 | $162.00 |
| 100 | $13.75 | $1,375.00 |
| 500 | $11.4 | $5,700.00 |
| 1,000 | $9.85 | $9,850.00 |
Drop-in alternatives for EPM7096LC84-15 β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
EPM7096LC84-10
β Drop-Inβ In Stock
$5.1 / Unit
View Datasheet βEPM7096LC84-7
β Drop-In β οΈ εζ°εΎ ιͺθ―β In Stock
$19.85 / Unit
View Datasheet βEPM7128SLC84-15
β Drop-Inπ Reference alternative (not in catalog)
EPM7128SLC84-10
β Drop-Inπ Reference alternative (not in catalog)
EPM7128ELC84-15
β Drop-Inπ Reference alternative (not in catalog)
EPM7096LC84-15 Maximum Ratings & Electrical Characteristics
| Family | MAX 7000 |
| Series | MAX 7000 (second-generation MAX architecture) |
| Macro Cells | 96 |
| Logic Array Blocks (LABs) | 4 |
| Usable Gates | 1,800 |
| Pin-to-Pin Propagation Delay (tPD) | 15 ns |
| Maximum Operating Frequency | 76.9 MHz |
| Supply Voltage (VCC) | 4.75 V to 5.25 V |
| Programmable Type | EE PLD (in-system programmable via JTAG) |
| Programming Interface | IEEE Std. 1149.1 JTAG |
| Operating Temperature | 0C to +70C (commercial) |
| Package / Case | 84-PLCC (J-Lead) |
| Supplier Device Package | 84-PLCC (29.31 x 29.31 mm) |
| Mounting Type | Surface Mount |
EPM7096LC84-15 Pin Configuration
| Pin 1 | I/O β User I/O pin |
| Pin 2 | I/O β User I/O pin |
| Pin 3 | I/O β User I/O pin |
| Pin 4 | I/O β User I/O pin |
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| Pin 9 | I/O β User I/O pin |
| Pin 10 | I/O β User I/O pin |
| Pin 11 | I/O β User I/O pin |
| Pin 12 | GND β Ground |
| Pin 13 | I/O β User I/O pin |
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| Pin 20 | I/O β User I/O pin |
| Pin 21 | I/O β User I/O pin |
| Pin 22 | I/O β User I/O pin |
| Pin 23 | TCK β JTAG test clock |
| Pin 24 | I/O β User I/O pin |
| Pin 25 | TMS β JTAG test mode select |
| Pin 26 | I/O β User I/O pin |
| Pin 27 | TDI β JTAG test data in |
| Pin 28 | I/O β User I/O pin |
| Pin 29 | TDO β JTAG test data out |
| Pin 30 | I/O β User I/O pin |
| Pin 31 | I/O β User I/O pin |
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| Pin 37 | I/O β User I/O pin |
| Pin 38 | I/O β User I/O pin |
| Pin 39 | VCC β +5V supply |
| Pin 40 | I/O β User I/O pin |
| Pin 41 | I/O β User I/O pin |
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| Pin 64 | I/O β User I/O pin |
| Pin 65 | I/O β User I/O pin |
| Pin 66 | I/O β User I/O pin |
| Pin 67 | GND β Ground |
| Pin 68 | I/O β User I/O pin |
| Pin 69 | I/O β User I/O pin |
| Pin 70 | I/O β User I/O pin |
| Pin 71 | I/O β User I/O pin |
| Pin 72 | I/O β User I/O pin |
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| Pin 80 | I/O β User I/O pin |
| Pin 81 | I/O β User I/O pin |
| Pin 82 | I/O β User I/O pin |
| Pin 83 | INPUT/GCLK1 β Global clock / dedicated input |
| Pin 84 | I/O β User I/O pin |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM7096LC84-15 is suitable for 6 applications: Microcontroller Bus Interface Bridging, High-Speed Address Decoding, State-Machine Based Motor Control, Legacy Peripheral Expansion, JTAG-Controlled Test and Boundary-Scan Infrastructure, Telecom Backplane Glue Logic.
Microcontroller Bus Interface Bridging
The EPM7096LC84-15 is widely used as a glue-logic bridge between legacy 8-bit or 16-bit microcontrollers and 32-bit peripheral buses, where deterministic timing and 5V I/O tolerance are required. With 96 macrocells and 68 user I/O, the device can implement address decoders, chip-select generators, and wait-state insertion logic on a single non-volatile chip. The 15 ns pin-to-pin delay at 76.9 MHz fMAX comfortably meets the timing requirements of ISA, PC/104, and standard memory-mapped peripheral buses up to 33 MHz. Unlike a small FPGA, the EPM7096LC84-15 boots instantly from its internal EEPROM at power-up with no external configuration memory required, simplifying board layout. Pair with a 5V-tolerant MCU such as the Intel 8051 family or NXP 80C51 derivatives.
Recommended
High-Speed Address Decoding
The EPM7096LC84-15 excels at high-speed address decoding for memory and peripheral chip-select generation in 16-bit and 32-bit systems, where its 15 ns propagation delay is well within one bus cycle of most legacy microprocessors. The 96 macrocells comfortably accommodate multi-bank memory maps with separate chip selects for ROM, RAM, and peripherals, including upper/lower byte enables and write strobes. With four Logic Array Blocks and 68 I/O, the device supports wide address buses (up to A23) plus control signals on a single device. The deterministic interconnect delay means decode timing is independent of how many other functions are placed in the device, simplifying static-timing analysis compared to FPGA-based decoders.
Recommended
State-Machine Based Motor Control
The EPM7096LC84-15 is frequently deployed in industrial motor and actuator control subsystems, where its 5V tolerant I/O interfaces directly with industrial-grade Hall-effect sensors, optocouplers, and 24V-driver logic via external level shifters. With 96 macrocells, the CPLD can implement multi-state commutation tables, fault-recovery sequences, and PWM-edge timing logic without CPU intervention. The 15 ns propagation delay supports PWM frequencies up to 76.9 kHz with sub-microsecond dead-time insertion, adequate for brushed-DC and stepper control loops. The MAX 7000 EEPROM core survives brown-outs and vibration-induced power glitches, making the EPM7096LC84-15 attractive for rugged industrial environments where FPGAs with volatile SRAM configuration would risk corruption.
Recommended
Legacy Peripheral Expansion
Designers extending the life of legacy equipment use the EPM7096LC84-15 to add modern peripheral interfaces (USB, I2C, SPI bridges) to old microprocessor platforms that lack native support. The CPLD's JTAG ISP allows field firmware updates without removing boards, while the 68 user I/O pins provide ample headroom for multi-interface glue logic. With 1,800 usable gates, the device can host protocol converters, parallel-to-serial serializers, and interrupt controllers on a single non-volatile device. The 5V tolerance makes the EPM7096LC84-15 a natural fit for interfacing with 5V peripherals in VMEbus, Multibus, and STD-32 legacy systems still common in industrial and military applications.
Recommended
JTAG-Controlled Test and Boundary-Scan Infrastructure
The EPM7096LC84-15's built-in IEEE 1149.1 JTAG interface makes it a natural boundary-scan master for legacy boards that lack dedicated test access ports. Designers can chain the CPLD into the board's JTAG topology to provide inter-board interconnect testing, cluster pin continuity checks, and ISP routing for downstream MAX 7000 family devices. With 96 macrocells the device can implement a TAP controller state machine, instruction register, and Bypass/Extest/Sample/Preload instructions on a single chip. The 5V tolerance means it can drive long backplane JTAG chains in telecom and industrial backplanes without external buffering, simplifying test fixture design for manufacturing.
Recommended
Telecom Backplane Glue Logic
The EPM7096LC84-15 is well suited to telecom backplane applications where it serves as bus arbiter, parity generator/checker, and frame-alignment logic for T1/E1 and older PDH/SDH framers. With 96 macrocells and 68 I/O, the device can implement multi-drop bus arbitration, hot-swap control sequencing, and alarm-status aggregation across a backplane. The 5V I/O tolerance interfaces directly with legacy bus driver/receiver ICs without external level translation. The MAX 7000 architecture's deterministic 15 ns propagation delay guarantees bus arbitration timing independent of logic placement, a critical property for multi-card backplane systems where FPGAs could introduce timing variability between cards.
Recommended
Recommended Products Summary
Engineering reference data for EPM7096LC84-15 β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM7096LC84-10 | EPM7096LC84-7 | EPM7128SLC84-15 | EPM7128SLC84-10 | EPM7128ELC84-15 |
|---|---|---|---|---|---|---|
| Package | 84-PLCC | 84-PLCC - same | 84-PLCC - same | 84-PLCC - same | 84-PLCC - same | 84-PLCC - same |
| Brand | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) |
| Macro Cells | 96 | 96 | 96 | 128 | 128 | 128 |
| Logic Array Blocks | 4 | 4 | 4 | 8 | 8 | 8 |
| Usable Gates | 1,800 | 1,800 | 1,800 | 2,500 | 2,500 | 2,500 |
| Pin-to-Pin Delay (tPD) | 15 ns | 10 ns (-33%) | 7.5 ns (-50%) | 15 ns (0%) | 10 ns (-33%) | 15 ns (0%) |
| Max Frequency | 76.9 MHz | 100 MHz | 125 MHz | 76.9 MHz | 100 MHz | [DATA_NEEDED] |
| Supply Voltage | 4.75V - 5.25V | 4.75V - 5.25V | 4.75V - 5.25V | 4.75V - 5.25V | 4.75V - 5.25V | 3.0V - 3.6V (3.3V core) |
| User I/O | 68 | 68 | 68 | 68 | 68 | 68 |
Key Differentiators
- Lowest-cost MAX 7000 speed grade in 84-PLCC (vs EPM7096LC84-10)
- 5V VCC compatibility for legacy systems (vs EPM7128ELC84-15)
- 96 macrocells in compact 84-PLCC with 68 I/O (vs EPM7096LC68-15)
Design Notes
Per the MAX 7000 datasheet, VCC must rise monotonically during power-up to ensure proper configuration of the internal EEPROM-based logic. Use a 0.1uF ceramic decoupling capacitor within 5mm of each VCC pin and a 10uF tantalum bulk capacitor near the package to suppress supply transients. The EPM7096LC84-15 draws up to approximately 300mA ICC during operation (exact value not in verified web data - verify with MAX 7000 datasheet). Ensure that the 5V rail has less than 100mV peak-to-peak ripple to avoid logic errors during in-system programming.
The 84-pin PLCC package has a 1.27mm pitch and is supplied in J-lead surface-mount form. Use a PLCC socket (e.g., 3M Textool or similar) for development boards to allow device swap-out during design iteration, or solder directly with careful thermal profile control during reflow. All unused I/O pins should be left floating or tied to GND via 10k ohm resistors to prevent oscillation - the MAX 7000 family does not have internal weak pull-ups on unused pins. JTAG pins TCK, TMS, TDI, TDO must be terminated properly per IEEE 1149.1 with 10k ohm pull-ups on TMS and TDI.
The EPM7096LC84-15 is rated for 100 minimum erase/program cycles - do not use it in field-deployed systems requiring frequent firmware updates via JTAG. Voltage undershoot below -0.5V is not permitted; during transitions inputs may undershoot to -2.0V for input currents less than 100mA and periods shorter than 20ns without damage - verify worst-case undershoot on any high-speed switching signal entering the CPLD. Avoid mixing 5V MAX 7000 LC series parts with 3.3V ELC series parts on the same VCC rail, as their supply rails are incompatible and will damage the lower-voltage device.
The EPM7096LC84-15 supports 5V-tolerant inputs but does not have 5V-tolerant outputs on all pins - check the MAX 7000 datasheet pin table before driving 5V signals into a 3.3V peripheral. Series-terminate clock inputs (TCK, GCLK1) with 33 ohm resistors near the driver to control ringing on long traces. For high-speed JTAG chains (>6 inches), buffer TCK and TMS at the source and at each CPLD to maintain signal integrity.
Compliance Information
Compliance information not present in the verified web data - the EPM7096LC84-15 predates RoHS standardization in many datasheets. Marked as 'unknown' rather than assumed. Original MAX 7000 datasheet published October 1998; AEC-Q100 not applicable as this is a commercial-grade CPLD.
