EPM7128SLC84-7N vs EPM7128SLI84-10N Comparison

Detailed side-by-side comparison of EPM7128SLC84-7N by Intel and EPM7128SLI84-10N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM7128SLC84-7N EPM7128SLI84-10N
Brand Intel Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete NRND
Series MAX 7000S —
Programmable Type In System Programmable (ISP) —
Memory Type EEPROM —
Number of Macrocells 128 —
Number of Logic Elements/Blocks 8 (Logic Array Blocks) —
Number of Usable Gates 2,500 —
Number of I/O Pins 68 —
Propagation Delay (tpd) Max 7.5 ns —
Maximum Operating Frequency 125 MHz —
Counter Speed (Internal) up to 175.4 MHz (family max) —
Supply Voltage (VCCINT) 4.75 V to 5.25 V (5 V nominal) 4.75 V to 5.25 V (5 V typical)
Operating Temperature 0 C to +70 C (Commercial) -40 C to +85 C (Industrial)
Package 84-LCC (J-Lead), PLCC-84 84-pin PLCC (J-Lead)
Mounting Type Surface Mount Surface Mount
MSL Level [DATA_NEEDED: MSL level] —
RoHS Status Compliant (lead-free 'N' suffix) [DATA_NEEDED: RoHS compliance per latest Intel/Altera declaration]
Family — MAX 7000S
Logic Cells / Macro Cells — 128 macro cells
Usable Gates — 2,500
Number of Logic Elements / Blocks — 16 Logic Array Blocks (LABs)
User I/Os — 68
Propagation Delay (tPD) — 10 ns
Maximum Frequency (fMAX) — 125 MHz
I/O Voltage Tolerance — 3.3 V / 5 V MultiVolt I/O
Process Technology — CMOS EEPROM
Programmability — In-system programmable (ISP), non-volatile EEPROM
Boundary-Scan (JTAG) — IEEE Std 1149.1 compliant
Lead-Free — [DATA_NEEDED: lead-free per latest Intel/Altera declaration]

Datasheets & Resources

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