EPM7128SLC84-7N vs EPM7128SLI84-10N 比較
詳細並排比較 EPM7128SLC84-7N 由 Intel 與 EPM7128SLI84-10N 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
Altera
EPM7128SLI84-10N - MAX 7000S CPLD 128 Macro 10ns 84-PLCC | Intel / Altera
EPM7128SLI84-10N Nrnd規格比較
| 參數 | EPM7128SLC84-7N | EPM7128SLI84-10N |
|---|---|---|
| 品牌 | Intel | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | NRND |
| Series | MAX 7000S | — |
| Programmable Type | In System Programmable (ISP) | — |
| 記憶體類型 | EEPROM | — |
| Number of Macrocells | 128 | — |
| Number of Logic Elements/Blocks | 8 (Logic Array Blocks) | — |
| Number of Usable Gates | 2,500 | — |
| Number of I/O Pins | 68 | — |
| Propagation Delay (tpd) Max | 7.5 ns | — |
| Maximum Operating Frequency | 125 MHz | — |
| Counter Speed (Internal) | up to 175.4 MHz (family max) | — |
| Supply Voltage (VCCINT) | 4.75 V to 5.25 V (5 V nominal) | 4.75 V to 5.25 V (5 V typical) |
| 工作溫度 | 0 C to +70 C (Commercial) | -40 C to +85 C (Industrial) |
| 封裝 | 84-LCC (J-Lead), PLCC-84 | 84-pin PLCC (J-Lead) |
| 安裝類型 | Surface Mount | Surface Mount |
| MSL 等級 | [DATA_NEEDED: MSL level] | — |
| RoHS 狀態 | Compliant (lead-free 'N' suffix) | [DATA_NEEDED: RoHS compliance per latest Intel/Altera declaration] |
| Family | — | MAX 7000S |
| Logic Cells / Macro Cells | — | 128 macro cells |
| Usable Gates | — | 2,500 |
| Number of Logic Elements / Blocks | — | 16 Logic Array Blocks (LABs) |
| User I/Os | — | 68 |
| Propagation Delay (tPD) | — | 10 ns |
| Maximum Frequency (fMAX) | — | 125 MHz |
| I/O Voltage Tolerance | — | 3.3 V / 5 V MultiVolt I/O |
| Process Technology | — | CMOS EEPROM |
| Programmability | — | In-system programmable (ISP), non-volatile EEPROM |
| Boundary-Scan (JTAG) | — | IEEE Std 1149.1 compliant |
| Lead-Free | — | [DATA_NEEDED: lead-free per latest Intel/Altera declaration] |