EPM7128SLC84-7N vs EPM7128SLI84-10N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM7128SLC84-7N sa pamamagitan ng Intel at EPM7128SLI84-10N sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Altera
EPM7128SLI84-10N - MAX 7000S CPLD 128 Macro 10ns 84-PLCC | Intel / Altera
EPM7128SLI84-10N NrndPagsanggunian na paghahambing
| Parametro | EPM7128SLC84-7N | EPM7128SLI84-10N |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | NRND |
| Series | MAX 7000S | — |
| Programmable Type | In System Programmable (ISP) | — |
| Uri ng Memory | EEPROM | — |
| Number of Macrocells | 128 | — |
| Number of Logic Elements/Blocks | 8 (Logic Array Blocks) | — |
| Number of Usable Gates | 2,500 | — |
| Number of I/O Pins | 68 | — |
| Propagation Delay (tpd) Max | 7.5 ns | — |
| Maximum Operating Frequency | 125 MHz | — |
| Counter Speed (Internal) | up to 175.4 MHz (family max) | — |
| Supply Voltage (VCCINT) | 4.75 V to 5.25 V (5 V nominal) | 4.75 V to 5.25 V (5 V typical) |
| Temperature na Operasyon | 0 C to +70 C (Commercial) | -40 C to +85 C (Industrial) |
| Packhaging | 84-LCC (J-Lead), PLCC-84 | 84-pin PLCC (J-Lead) |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Level ng MSL | [DATA_NEEDED: MSL level] | — |
| Tindminan RoHS | Compliant (lead-free 'N' suffix) | [DATA_NEEDED: RoHS compliance per latest Intel/Altera declaration] |
| Family | — | MAX 7000S |
| Logic Cells / Macro Cells | — | 128 macro cells |
| Usable Gates | — | 2,500 |
| Number of Logic Elements / Blocks | — | 16 Logic Array Blocks (LABs) |
| User I/Os | — | 68 |
| Propagation Delay (tPD) | — | 10 ns |
| Maximum Frequency (fMAX) | — | 125 MHz |
| I/O Voltage Tolerance | — | 3.3 V / 5 V MultiVolt I/O |
| Process Technology | — | CMOS EEPROM |
| Programmability | — | In-system programmable (ISP), non-volatile EEPROM |
| Boundary-Scan (JTAG) | — | IEEE Std 1149.1 compliant |
| Lead-Free | — | [DATA_NEEDED: lead-free per latest Intel/Altera declaration] |