EPM7128SQC100-6 vs EPM7128SQC100-15 Comparison
Detailed side-by-side comparison of EPM7128SQC100-6 by Intel and EPM7128SQC100-15 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM7128SQC100-15 - MAX 7000 CPLD 128MC 15ns 5V | Altera/Intel
EPM7128SQC100-15 ⚠ Last Time BuySpecification Comparison
| Parameter | EPM7128SQC100-6 | EPM7128SQC100-15 |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Active | Last Time Buy |
| Unit Price (USD) | — | $8.20 |
| Family | MAX 7000S | MAX 7000 |
| Logic Family | CMOS (EEPROM-based) | — |
| Macrocells | 128 | 128 |
| Usable Gates | 2,500 | — |
| User I/Os | 84 | 84 |
| Number of Pins | 100 | — |
| Package | PQFP-100 (SQC), 100-BQFP | 100-pin PQFP (Plastic Quad Flat Pack) |
| Propagation Delay (tPD) | 6 ns | — |
| Internal Frequency | 147.1 MHz | — |
| Supply Voltage | 5 V | — |
| Operating Temperature | 0C to +70C (commercial) | 0C to +70C (Commercial) |
| Programmable via | JTAG (IEEE 1149.1) ISP | — |
| Memory Type | Non-volatile EEPROM | — |
| Mounting Type | Surface Mount (Tray) | Surface Mount |
| RoHS Status | [DATA_NEEDED: rohs status] | Non-compliant (SnPb lead finish - legacy PQFP) |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Logic Array Blocks (LABs) | — | 4 (16 macrocells each) |
| Pin-to-Pin Delay (tPD) | — | 15 ns |
| Maximum Frequency (fMAX) | — | [DATA_NEEDED: fMAX value] |
| Typical Gate Count | — | 2,500 gates |
| Supply Voltage (VCCINT) | — | 5 V (5% tolerance) |
| Programming Technology | — | EEPROM (in-system programmable via JTAG) |
| JTAG Interface | — | IEEE Std. 1149.1 compliant |
| MSL Level | — | 3 (168 hours) |