EPM7128SQC100-6 vs EPM7128SQC100-15 Pengandingan
Pengandingan Sisi Kiri Sisi Kanan Terperinci EPM7128SQC100-6 disebabkan oleh Intel dan EPM7128SQC100-15 disebabkan oleh Altera. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.
Altera
EPM7128SQC100-15 - MAX 7000 CPLD 128MC 15ns 5V | Altera/Intel
EPM7128SQC100-15 ⚠ Bahagian terakhir untuk beliPengandingan Spesifikasi
| Parametr | EPM7128SQC100-6 | EPM7128SQC100-15 |
|---|---|---|
| Merek | Intel | Altera |
| Kategori | FPGA & CPLD | FPGA & CPLD |
| Status Lingkungan Hidup | Aktif | Masa Terakhir Dibeli |
| Harga Unit (USD) | — | $8.20 |
| Family | MAX 7000S | MAX 7000 |
| Logic Family | CMOS (EEPROM-based) | — |
| Macrocells | 128 | 128 |
| Usable Gates | 2,500 | — |
| User I/Os | 84 | 84 |
| Bilangan Pin | 100 | — |
| Kemasan | PQFP-100 (SQC), 100-BQFP | 100-pin PQFP (Plastic Quad Flat Pack) |
| Propagation Delay (tPD) | 6 ns | — |
| Internal Frequency | 147.1 MHz | — |
| Tegangan Pemberi Arus | 5 V | — |
| Suhu Operasi | 0C to +70C (commercial) | 0C to +70C (Commercial) |
| Programmable via | JTAG (IEEE 1149.1) ISP | — |
| Jenis Ingatan | Non-volatile EEPROM | — |
| Jenis Pemasangan | Surface Mount (Tray) | Surface Mount |
| Status RoHS | [DATA_NEEDED: rohs status] | Non-compliant (SnPb lead finish - legacy PQFP) |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Logic Array Blocks (LABs) | — | 4 (16 macrocells each) |
| Pin-to-Pin Delay (tPD) | — | 15 ns |
| Maximum Frequency (fMAX) | — | [DATA_NEEDED: fMAX value] |
| Typical Gate Count | — | 2,500 gates |
| Supply Voltage (VCCINT) | — | 5 V (5% tolerance) |
| Programming Technology | — | EEPROM (in-system programmable via JTAG) |
| JTAG Interface | — | IEEE Std. 1149.1 compliant |
| Aras MSL | — | 3 (168 hours) |