EPM7128SQI100-10N vs EPM7128SQI100-10 Comparison
Detailed side-by-side comparison of EPM7128SQI100-10N by Intel and EPM7128SQI100-10 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Intel
EPM7128SQI100-10N - 128-Macrocell MAX 7000S CPLD, 10ns, PQFP-100 | Intel / Altera
EPM7128SQI100-10N NrndAltera
EPM7128SQI100-10 - MAX 7000S CPLD 128-Macrocell 84-IO 10ns | Altera
EPM7128SQI100-10 ObsoleteSpecification Comparison
| Parameter | EPM7128SQI100-10N | EPM7128SQI100-10 |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Nrnd | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $15.90 | $9.75 |
| Family | MAX 7000S | MAX 7000S |
| Device Type | CPLD - Complex Programmable Logic Device | CPLD - Complex Programmable Logic Device |
| Macrocells | 128 | β |
| Usable Gates | 2,500 (up to 5,000 usable in family) | 2,500 |
| Logic Array Blocks (LABs) | 4 | β |
| Maximum User I/Os | 84 | β |
| Pin-to-Pin Logic Delay (tPD) | 10 ns | β |
| Maximum Operating Frequency | 100 MHz | β |
| Counter Frequency (family max) | 175.4 MHz | β |
| Supply Voltage - Core (VCCINT) | 5.0 V | β |
| Supply Voltage - I/O (VCCIO) | 2.5 V / 3.3 V / 5.0 V (multiVolt) | β |
| Technology | CMOS, EEPROM-based configuration | β |
| Package | 100-pin PQFP (Plastic Quad Flat Pack) | β |
| Mounting Type | Surface Mount | β |
| Operating Temperature | -40C to +85C (Industrial grade, 'I' suffix) | -40C to +85C (Industrial) |
| Programming Interface | JTAG (IEEE Std. 1149.1) / ByteBlaster | β |
| RoHS Compliance | Compliant (lead-free, 'N' suffix) | β |
| Macro Cells | β | 128 |
| User I/Os | β | 84 |
| Logic Blocks (LABs) | β | 8 (16 macrocells each) |
| Package Type | β | PQFP-100 |
| Pin-to-Pin Delay (tPD) | β | 10 ns |
| Maximum Internal Frequency | β | 125 MHz to 250 MHz |
| Counter Speed | β | Up to 175.4 MHz |
| Operating Voltage (VCC) | β | 5 V |
| Configuration Memory | β | EEPROM (non-volatile) |
| Program/Erase Cycles | β | 100 minimum |
| In-System Programming | β | Yes (JTAG IEEE 1149.1) |
| Logic Family | β | CMOS |
| I/O Compatibility | β | TTL-compatible, 5V/3.3V multi-voltage |
| RoHS Status | β | [DATA_NEEDED: RoHS status not in provided data] |