EPM7128SQI100-10N vs EPM7128SQI100-10 Comparaison
Comparaison détaillée côte à côte de EPM7128SQI100-10N par Intel et EPM7128SQI100-10 par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Intel
EPM7128SQI100-10N - 128-Macrocell MAX 7000S CPLD, 10ns, PQFP-100 | Intel / Altera
EPM7128SQI100-10N NrndAltera
EPM7128SQI100-10 - MAX 7000S CPLD 128-Macrocell 84-IO 10ns | Altera
EPM7128SQI100-10 ObsoleteComparaison des spécifications
| Paramètre | EPM7128SQI100-10N | EPM7128SQI100-10 |
|---|---|---|
| Marque | Intel | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | NRND | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $15,90 | $9,75 |
| Family | MAX 7000S | MAX 7000S |
| Device Type | CPLD - Complex Programmable Logic Device | CPLD - Complex Programmable Logic Device |
| Macrocells | 128 | — |
| Usable Gates | 2,500 (up to 5,000 usable in family) | 2,500 |
| Logic Array Blocks (LABs) | 4 | — |
| Maximum User I/Os | 84 | — |
| Pin-to-Pin Logic Delay (tPD) | 10 ns | — |
| Maximum Operating Frequency | 100 MHz | — |
| Counter Frequency (family max) | 175.4 MHz | — |
| Supply Voltage - Core (VCCINT) | 5.0 V | — |
| Supply Voltage - I/O (VCCIO) | 2.5 V / 3.3 V / 5.0 V (multiVolt) | — |
| Technology | CMOS, EEPROM-based configuration | — |
| Boîtier | 100-pin PQFP (Plastic Quad Flat Pack) | — |
| Type de montage | Surface Mount | — |
| Température de fonctionnement | -40C to +85C (Industrial grade, 'I' suffix) | -40C to +85C (Industrial) |
| Programming Interface | JTAG (IEEE Std. 1149.1) / ByteBlaster | — |
| RoHS Compliance | Compliant (lead-free, 'N' suffix) | — |
| Macro Cells | — | 128 |
| User I/Os | — | 84 |
| Logic Blocks (LABs) | — | 8 (16 macrocells each) |
| Package Type | — | PQFP-100 |
| Pin-to-Pin Delay (tPD) | — | 10 ns |
| Maximum Internal Frequency | — | 125 MHz to 250 MHz |
| Counter Speed | — | Up to 175.4 MHz |
| Operating Voltage (VCC) | — | 5 V |
| Configuration Memory | — | EEPROM (non-volatile) |
| Program/Erase Cycles | — | 100 minimum |
| In-System Programming | — | Yes (JTAG IEEE 1149.1) |
| Logic Family | — | CMOS |
| I/O Compatibility | — | TTL-compatible, 5V/3.3V multi-voltage |
| Statut RoHS | — | [DATA_NEEDED: RoHS status not in provided data] |