EPM7128SQI100-10N vs EPM7128SQI100-10 对比

详细并排对比 EPM7128SQI100-10N 出自 Intel 和 EPM7128SQI100-10 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPM7128SQI100-10N EPM7128SQI100-10
品牌 Intel Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 不推荐新设计 Obsolete
库存状态 有库存 有库存
单价(USD) $15.90 $9.75
Family MAX 7000S MAX 7000S
Device Type CPLD - Complex Programmable Logic Device CPLD - Complex Programmable Logic Device
Macrocells 128 —
Usable Gates 2,500 (up to 5,000 usable in family) 2,500
Logic Array Blocks (LABs) 4 —
Maximum User I/Os 84 —
Pin-to-Pin Logic Delay (tPD) 10 ns —
Maximum Operating Frequency 100 MHz —
Counter Frequency (family max) 175.4 MHz —
Supply Voltage - Core (VCCINT) 5.0 V —
Supply Voltage - I/O (VCCIO) 2.5 V / 3.3 V / 5.0 V (multiVolt) —
Technology CMOS, EEPROM-based configuration —
封装 100-pin PQFP (Plastic Quad Flat Pack) —
安装类型 Surface Mount —
工作温度 -40C to +85C (Industrial grade, 'I' suffix) -40C to +85C (Industrial)
Programming Interface JTAG (IEEE Std. 1149.1) / ByteBlaster —
RoHS Compliance Compliant (lead-free, 'N' suffix) —
Macro Cells — 128
User I/Os — 84
Logic Blocks (LABs) — 8 (16 macrocells each)
Package Type — PQFP-100
Pin-to-Pin Delay (tPD) — 10 ns
Maximum Internal Frequency — 125 MHz to 250 MHz
Counter Speed — Up to 175.4 MHz
Operating Voltage (VCC) — 5 V
Configuration Memory — EEPROM (non-volatile)
Program/Erase Cycles — 100 minimum
In-System Programming — Yes (JTAG IEEE 1149.1)
Logic Family — CMOS
I/O Compatibility — TTL-compatible, 5V/3.3V multi-voltage
RoHS 状态 — [DATA_NEEDED: RoHS status not in provided data]

数据手册与资源

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