EPM7128STC100-15N - 128-Macro Cell CPLD, 15ns, 100-TQFP | Intel / Altera
MPN: EPM7128STC100-15N β End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $15.02 | $15.02 |
| 10 | $13.5 | $135.00 |
| 100 | $11.85 | $1,185.00 |
| 500 | $10.4 | $5,200.00 |
| 1,000 | $9.2 | $9,200.00 |
Drop-in alternatives for EPM7128STC100-15N β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
EPM7128STC100-15
β Drop-Inπ Reference alternative (not in catalog)
EPM7128STC100-10N
β Drop-Inβ In Stock
$9.3 / Unit
View Datasheet βEPM7128SQC100-10N
β Drop-Inβ In Stock
$14.95 / Unit
View Datasheet βEPM7128SQC100-10
β Drop-Inβ In Stock
$9.85 / Unit
View Datasheet βEPM7128SQC100-15
β Drop-Inβ In Stock
$8.2 / Unit
View Datasheet βEPM7128SQC100-7N
β Drop-Inβ In Stock
$7.1 / Unit
View Datasheet βEPM7128STC100-15N Maximum Ratings & Electrical Characteristics
| Product Type | CPLD (Complex Programmable Logic Device) |
| Family | MAX 7000S |
| Usable Gates | 2,500 |
| Macro Cells | 128 |
| Logic Array Blocks (LABs) | 8 (16 macro cells each) |
| Maximum User I/O | 84 |
| Pin-to-Pin Logic Delay (tPD) | 15 ns (-15 speed grade) |
| Maximum Internal Frequency | 76.9 MHz |
| Supply Voltage (VCC) | 5 V (4.75 V to 5.25 V) |
| Supply Voltage (VCCIO) | 3.3 V or 5 V (per bank) |
| Technology | CMOS EEPROM, in-system programmable |
| Package | 100-pin TQFP |
| Operating Temperature | 0C to +70C (commercial) |
| JTAG (IEEE 1149.1) | Yes - in-system programming |
| Output Options | Totem-pole or open-drain (per pin) |
| Dedicated Inputs | 4 global inputs |
| RoHS Status | Non-RoHS (legacy SnPb finish typical) |
| Lifecycle Status | Obsolete (PDN effective 2017-06-01) |
EPM7128STC100-15N Pin Configuration
| Pin 1 | GLOBAL_CLK1 β Global clock input 1 (dedicated) |
| Pin 2 | I/O β User I/O pin |
| Pin 3 | I/O β User I/O pin |
| Pin 4 | I/O β User I/O pin |
| Pin 5 | I/O β User I/O pin |
| Pin 6 | I/O β User I/O pin |
| Pin 7 | I/O β User I/O pin |
| Pin 8 | I/O β User I/O pin |
| Pin 9 | I/O β User I/O pin |
| Pin 10 | I/O β User I/O pin |
| Pin 11 | I/O β User I/O pin |
| Pin 12 | I/O β User I/O pin |
| Pin 13 | I/O β User I/O pin |
| Pin 14 | GND β Ground |
| Pin 15 | I/O β User I/O pin |
| Pin 16 | I/O β User I/O pin |
| Pin 17 | I/O β User I/O pin |
| Pin 18 | I/O β User I/O pin |
| Pin 19 | I/O β User I/O pin |
| Pin 20 | I/O β User I/O pin |
| Pin 21 | I/O β User I/O pin |
| Pin 22 | I/O β User I/O pin |
| Pin 23 | I/O β User I/O pin |
| Pin 24 | I/O β User I/O pin |
| Pin 25 | GND β Ground |
| Pin 26 | I/O β User I/O pin |
| Pin 27 | I/O β User I/O pin |
| Pin 28 | I/O β User I/O pin |
| Pin 29 | I/O β User I/O pin |
| Pin 30 | I/O β User I/O pin |
| Pin 31 | I/O β User I/O pin |
| Pin 32 | I/O β User I/O pin |
| Pin 33 | I/O β User I/O pin |
| Pin 34 | I/O β User I/O pin |
| Pin 35 | I/O β User I/O pin |
| Pin 36 | I/O β User I/O pin |
| Pin 37 | I/O β User I/O pin |
| Pin 38 | GND β Ground |
| Pin 39 | I/O β User I/O pin |
| Pin 40 | I/O β User I/O pin |
| Pin 41 | I/O β User I/O pin |
| Pin 42 | I/O β User I/O pin |
| Pin 43 | I/O β User I/O pin |
| Pin 44 | I/O β User I/O pin |
| Pin 45 | I/O β User I/O pin |
| Pin 46 | I/O β User I/O pin |
| Pin 47 | I/O β User I/O pin |
| Pin 48 | TDI β JTAG Test Data In |
| Pin 49 | TMS β JTAG Test Mode Select |
| Pin 50 | TCK β JTAG Test Clock |
| Pin 51 | GND β Ground |
| Pin 52 | I/O β User I/O pin |
| Pin 53 | I/O β User I/O pin |
| Pin 54 | I/O β User I/O pin |
| Pin 55 | I/O β User I/O pin |
| Pin 56 | I/O β User I/O pin |
| Pin 57 | I/O β User I/O pin |
| Pin 58 | I/O β User I/O pin |
| Pin 59 | I/O β User I/O pin |
| Pin 60 | I/O β User I/O pin |
| Pin 61 | I/O β User I/O pin |
| Pin 62 | I/O β User I/O pin |
| Pin 63 | GND β Ground |
| Pin 64 | I/O β User I/O pin |
| Pin 65 | I/O β User I/O pin |
| Pin 66 | I/O β User I/O pin |
| Pin 67 | I/O β User I/O pin |
| Pin 68 | I/O β User I/O pin |
| Pin 69 | I/O β User I/O pin |
| Pin 70 | I/O β User I/O pin |
| Pin 71 | I/O β User I/O pin |
| Pin 72 | I/O β User I/O pin |
| Pin 73 | I/O β User I/O pin |
| Pin 74 | I/O β User I/O pin |
| Pin 75 | I/O β User I/O pin |
| Pin 76 | GND β Ground |
| Pin 77 | I/O β User I/O pin |
| Pin 78 | I/O β User I/O pin |
| Pin 79 | I/O β User I/O pin |
| Pin 80 | I/O β User I/O pin |
| Pin 81 | I/O β User I/O pin |
| Pin 82 | I/O β User I/O pin |
| Pin 83 | I/O β User I/O pin |
| Pin 84 | I/O β User I/O pin |
| Pin 85 | I/O β User I/O pin |
| Pin 86 | I/O β User I/O pin |
| Pin 87 | I/O β User I/O pin |
| Pin 88 | I/O β User I/O pin |
| Pin 89 | GND β Ground |
| Pin 90 | I/O β User I/O pin |
| Pin 91 | I/O β User I/O pin |
| Pin 92 | I/O β User I/O pin |
| Pin 93 | I/O β User I/O pin |
| Pin 94 | I/O β User I/O pin |
| Pin 95 | I/O β User I/O pin |
| Pin 96 | I/O β User I/O pin |
| Pin 97 | I/O β User I/O pin |
| Pin 98 | I/O β User I/O pin |
| Pin 99 | TDO β JTAG Test Data Out |
| Pin 100 | VCC β +5 V core supply |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM7128STC100-15N is suitable for 6 applications: Microcontroller I/O Expansion and Bus Decoding, Peripheral Glue Logic and Interface Bridging, State Machine and Industrial Control Logic, LED Multiplexing and Display Driving, Legacy 74LS / 74HC Logic Replacement, Instant-On Boot and Configuration Memory Replacement.
Microcontroller I/O Expansion and Bus Decoding
The EPM7128STC100-15N is a natural fit for microcontroller I/O expansion and bus decoding because its 128 macro cells and 84 user I/O pins can decode large address windows and generate multiple chip-select signals in a single device. The 15 ns pin-to-pin delay matches the timing budget of an 8-bit or 16-bit MCU running at 33 MHz, ensuring that the CPLD output settles within one clock period after the address bus changes. With 5 V VCCIO tolerance, the part can be interfaced directly to legacy 5 V peripherals without level-shifters, reducing BOM cost and board area. Designers typically implement address latch, chip-select decoding, and wait-state generation in one EPM7128, replacing multiple discrete 74LS138/74LS139 decoders and 74LS373 latches. The non-volatile EEPROM configuration boots in microseconds, so there is no FPGA-style configuration delay - critical for deterministic interrupt latency in motor-control or industrial-automation firmware.
Recommended
Peripheral Glue Logic and Interface Bridging
The EPM7128STC100-15N's deterministic timing and 5 V I/O make it ideal for interface-bridging glue logic between processors, memory, and peripherals operating at different voltages. A common use case is bridging a 5 V MCU to a 3.3 V SD card or NOR flash, where the CPLD's programmable VCCIO bank can be split into one 5 V bank and one 3.3 V bank - eliminating external level-shifters. The 15 ns tPD adds only one extra clock of latency at 66 MHz, which is acceptable for SPI, I2C, or parallel-memory interfaces. The 84 user I/Os are sufficient to implement a full 16-bit address bus, 16-bit data bus, and 8-10 control signals in a single device, leaving macro cells available for handshake logic. Designers also appreciate that the JTAG ISP allows field-upgradeable firmware fixes without desoldering the part.
Recommended
State Machine and Industrial Control Logic
For industrial control, the EPM7128STC100-15N's -15 ns delay, 76.9 MHz internal toggle rate, and EEPROM-based non-volatile configuration deliver the determinism and reliability required for safety-critical state machines. Each macro cell contains a flip-flop, so a single device can implement several independent FSMs such as a packaging-machine sequencer, conveyor controller, or HVAC state controller. The 5 V tolerant I/O interfaces directly to 24 V industrial sensors and actuators through external optocouplers, avoiding the level-shifting required by 3.3 V FPGAs. The MAX 7000S family's instant-on configuration (microseconds, not milliseconds) is critical for fail-safe startup where any boot delay could cause process malfunction. Programming via JTAG also lets engineers perform in-circuit firmware revisions without removing boards from production equipment.
Recommended
LED Multiplexing and Display Driving
The EPM7128STC100-15N's 84 user I/Os are well-suited for driving large LED matrices, 7-segment displays, and character LCDs where many discrete signals must be time-multiplexed. A single EPM7128 can scan a 64-LED matrix, an 8-digit 7-segment display, or a 4-line character LCD without any additional drivers. The 76.9 MHz internal toggle rate ensures flicker-free refresh rates above 100 Hz even for large displays, while the 15 ns tPD ensures clean column-to-column transitions. The 5 V I/O can directly drive common-anode or common-cathode LED arrays without buffer transistors, reducing board complexity. Designers also use the JTAG ISP to change display patterns or timing parameters without re-spinning hardware - a major advantage for prototype and small-batch production.
Recommended
Legacy 74LS / 74HC Logic Replacement
The EPM7128STC100-15N is frequently used to replace multiple discrete 74LS, 74HC, or 74HCT logic ICs on legacy PCBs where board area is constrained. A single EPM7128 can absorb up to 128 macro cells of glue logic - equivalent to 8-12 small-scale integration (SSI) packages - reducing both component count and assembly cost. The -15 ns tPD is comparable to a 74LS153 multiplexer or 74LS138 decoder, so existing timing margins are preserved. The 5 V VCCIO tolerance is pin-compatible with TTL and CMOS legacy logic rails, simplifying migration. This application is especially common in industrial and aerospace systems that must be re-spun to reduce obsolete-discrete-logic risk without redesigning the board footprint.
Recommended
Instant-On Boot and Configuration Memory Replacement
The EPM7128STC100-15N's EEPROM-based configuration cell provides microsecond-class instant-on, which is faster than any SRAM-based FPGA boot PROM. Designers use this property for power-critical applications such as automotive body controllers, security panels, and emergency-stop controllers where any boot delay is unacceptable. The 128 macro cells are sufficient to implement both the boot logic and the steady-state functionality in one device, eliminating a separate configuration memory chip. The JTAG ISP supports in-the-field firmware updates, so the same hardware can be reprogrammed across product variants - a major simplification for low-volume, high-mix production. Per the Altera datasheet, the configuration EEPROM retains the bitstream indefinitely without power, supporting decades of shelf life.
Recommended
Recommended Products Summary
Engineering reference data for EPM7128STC100-15N β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM7128STC100-15 | EPM7128STC100-10N | EPM7128SQC100-10N | EPM7128SQC100-15 |
|---|---|---|---|---|---|
| Brand | Intel (formerly Altera) | Intel (formerly Altera) | Intel (formerly Altera) | Intel (formerly Altera) | Intel (formerly Altera) |
| Package | 100-pin TQFP | 100-pin TQFP (same) | 100-pin TQFP (same) | 100-pin TQFP (same) | 100-pin TQFP (same) |
| Family / Sub-family | MAX 7000S | MAX 7000S | MAX 7000S | MAX 7000S | MAX 7000S |
| Pin-to-Pin Delay (tPD) | 15 ns | 15 ns (identical) | 10 ns (-33%) | 10 ns (-33%) | 15 ns (identical) |
| Macro Cells | 128 | 128 (identical) | 128 (identical) | 128 (identical) | 128 (identical) |
| Maximum Internal Frequency | 76.9 MHz | 76.9 MHz (identical) | 100 MHz (+30%) | 100 MHz (+30%) | 76.9 MHz (identical) |
| Usable Gates | 2,500 | 2,500 (identical) | 2,500 (identical) | 2,500 (identical) | 2,500 (identical) |
| User I/O Pins | 84 | 84 (identical) | 84 (identical) | 84 (identical) | 84 (identical) |
| Lead-Free Finish | Yes (Pb-free suffix 'N') | No (SnPb standard) | Yes (Pb-free) | Yes (Pb-free, PQFP) | No (SnPb, PQFP) |
| Operating Temperature | 0C to +70C (commercial) | 0C to +70C | 0C to +70C | 0C to +70C | 0C to +70C |
Key Differentiators
- Instant-on non-volatile EEPROM configuration (microseconds) (vs EPM7128SQC100-10N)
- Same-die drop-in availability in PQFP finish (EPM7128SQC100-10N) (vs EPM7128STC100-15)
- 128 macro cells / 84 I/Os in single 100-pin TQFP (vs EPM7128SLC84-10)
Design Notes
Estimated: at VCC = 5 V and all 84 I/Os toggling at 76.9 MHz into 50 pF loads, the EPM7128STC100-15N consumes approximately 250-400 mA of dynamic supply current plus 5-10 mA of static current. Designers should provide a 100 nF decoupling capacitor within 5 mm of each VCC pin (the 100-pin TQFP has multiple VCC pins distributed around the package). Per the Altera datasheet, unused I/O pins must be programmed as outputs driving ground to minimize switching current; leaving them floating can increase supply current by 30-50 mA.
Route all four JTAG signals (TCK, TMS, TDI, TDO) as a daisy-chain with 100 ohm series-termination resistors near the driving CPLD. Keep JTAG traces at least 3 mm away from clock traces to avoid coupling that can corrupt ISP programming. The exposed thermal pad of the 100-pin TQFP must be soldered to a copper pour of at least 1 square inch to keep junction temperature below 125 C at full toggle rate. Per the Altera datasheet, the VCCIO pins (5 V or 3.3 V) must be applied before VCC during power-up to prevent I/O latch-up.
Do not assume the EPM7128STC100-15N is in production - it was discontinued in June 2017 per the Altera PDN. Source from franchised distributors only (DigiKey, Mouser, Arrow) or from authorized secondary-market specialists. Verify that the JTAG chain order matches your schematic when chaining multiple EPM7xxx devices, because the MAX 7000S family uses a fixed 10-bit JTAG instruction register length. When migrating to MAX II / MAX V for new designs, plan for pinout differences and recompile all design files - the new families use a different BSDL boundary-scan description.
Compliance Information
Per the Altera datasheet, the EPM7128STC100-15N ships with a standard SnPb finish (non-lead-free). It is not AEC-Q100 qualified. RoHS-compliant variants are the EPM7128STC100-10N, EPM7128SQC100-10N, and EPM7128SQC100-7N (lead-free finishes).
