EPM7128STC100-15N vs EPM7128STC100-10 Comparison
Detailed side-by-side comparison of EPM7128STC100-15N by Intel and EPM7128STC100-10 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Intel
EPM7128STC100-15N
EPM7128STC100-15N - 128-Macro Cell CPLD, 15ns, 100-TQFP | Intel / Altera
EPM7128STC100-15N ObsoleteAltera
EPM7128STC100-10
EPM7128STC100-10 - 128-Macro MAX 7000S CPLD, 10ns TQFP-100 | Intel / Altera
EPM7128STC100-10 ObsoleteSpecification Comparison
| Parameter | EPM7128STC100-15N | EPM7128STC100-10 |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $9.20 | $7.10 |
| Product Type | CPLD (Complex Programmable Logic Device) | β |
| Family | MAX 7000S | MAX 7000S |
| Usable Gates | 2,500 | 2,500 |
| Macro Cells | 128 | 128 |
| Logic Array Blocks (LABs) | 8 (16 macro cells each) | β |
| Maximum User I/O | 84 | β |
| Pin-to-Pin Logic Delay (tPD) | 15 ns (-15 speed grade) | β |
| Maximum Internal Frequency | 76.9 MHz | β |
| Supply Voltage (VCC) | 5 V (4.75 V to 5.25 V) | β |
| Supply Voltage (VCCIO) | 3.3 V or 5 V (per bank) | β |
| Technology | CMOS EEPROM, in-system programmable | β |
| Package | 100-pin TQFP | TQFP-100 (C100) |
| Operating Temperature | 0C to +70C (commercial) | 0C to +70C (commercial) |
| JTAG (IEEE 1149.1) | Yes - in-system programming | β |
| Output Options | Totem-pole or open-drain (per pin) | β |
| Dedicated Inputs | 4 global inputs | β |
| RoHS Status | Non-RoHS (legacy SnPb finish typical) | [DATA_NEEDED: RoHS compliance status not in provided data] |
| Lifecycle Status | Obsolete (PDN effective 2017-06-01) | β |
| Device Type | β | CPLD (Complex Programmable Logic Device) |
| User I/Os | β | 84 |
| Logic Array Blocks | β | 8 (16 macrocells per LAB) |
| Propagation Delay (tPD) | β | 10 ns |
| Internal Counter Frequency (fCNT) | β | 100 MHz |
| Logic Family | β | CMOS |
| Supply Voltage (VCCINT) | β | 5 V |
| MultiVolt I/O Voltage | β | 3.3 V / 5 V |
| Pin Count | β | 100 |
| Mounting Type | β | Surface Mount |
| Programmability | β | In-System Programmable (JTAG, IEEE 1149.1), EEPROM |