EPM7128STC100-15N vs EPM7128STC100-10 Pengandingan

Pengandingan Sisi Kiri Sisi Kanan Terperinci EPM7128STC100-15N disebabkan oleh Intel dan EPM7128STC100-10 disebabkan oleh Altera. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.

Pengandingan Spesifikasi

Parametr EPM7128STC100-15N EPM7128STC100-10
Merek Intel Altera
Kategori FPGA & CPLD FPGA & CPLD
Status Lingkungan Hidup Obsolete Obsolete
Product Type CPLD (Complex Programmable Logic Device) —
Family MAX 7000S MAX 7000S
Usable Gates 2,500 2,500
Macro Cells 128 128
Logic Array Blocks (LABs) 8 (16 macro cells each) —
Maximum User I/O 84 —
Pin-to-Pin Logic Delay (tPD) 15 ns (-15 speed grade) —
Maximum Internal Frequency 76.9 MHz —
Supply Voltage (VCC) 5 V (4.75 V to 5.25 V) —
Supply Voltage (VCCIO) 3.3 V or 5 V (per bank) —
Technology CMOS EEPROM, in-system programmable —
Kemasan 100-pin TQFP TQFP-100 (C100)
Suhu Operasi 0C to +70C (commercial) 0C to +70C (commercial)
JTAG (IEEE 1149.1) Yes - in-system programming —
Output Options Totem-pole or open-drain (per pin) —
Dedicated Inputs 4 global inputs —
Status RoHS Non-RoHS (legacy SnPb finish typical) [DATA_NEEDED: RoHS compliance status not in provided data]
Status Lingkungan Hidup Obsolete (PDN effective 2017-06-01) —
Device Type — CPLD (Complex Programmable Logic Device)
User I/Os — 84
Logic Array Blocks — 8 (16 macrocells per LAB)
Propagation Delay (tPD) — 10 ns
Internal Counter Frequency (fCNT) — 100 MHz
Logic Family — CMOS
Supply Voltage (VCCINT) — 5 V
MultiVolt I/O Voltage — 3.3 V / 5 V
Kiraan Pin — 100
Jenis Pemasangan — Surface Mount
Programmability — In-System Programmable (JTAG, IEEE 1149.1), EEPROM

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