EPM7160ELC84-12 vs EPM7160ELC84-20 Comparison
Detailed side-by-side comparison of EPM7160ELC84-12 by Altera and EPM7160ELC84-20 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM7160ELC84-12 - MAX 7000 CPLD, 160 Macrocells, 12ns | Altera
EPM7160ELC84-12 β Last Time Buy
Specification Comparison
| Parameter | EPM7160ELC84-12 | EPM7160ELC84-20 |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Last_time_buy | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $11.10 | $16.95 |
| Manufacturer | Altera (Intel PSG) | β |
| Series | MAX 7000 (MAX 7000E) | β |
| Programmable Type | EE PLD (EEPROM) | β |
| Number of Macrocells | 160 | β |
| Number of Logic Array Blocks (LABs) | 4 | β |
| Number of Usable Gates | 3,200 | β |
| Number of I/O (max) | 68 | β |
| Number of I/O (per package) | 64 | β |
| Propagation Delay tpd(1) max | 12 ns | β |
| Counter Frequency (max) | 90.9 MHz | β |
| Voltage Supply - Internal | 4.75 V to 5.25 V (5 V nominal) | β |
| Operating Temperature | 0C to +70C (commercial) | β |
| Package / Case | 84-LCC (J-Lead) | β |
| Supplier Device Package | 84-PLCC (29.31 x 29.31 mm) | β |
| Mounting Type | Surface Mount | Surface Mount (PLCC socket compatible) |
| In-System Programmability | Yes (IEEE 1149.1 JTAG) | β |
| RoHS Status | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS compliance per specific part marking] |
| Family | β | MAX 7000 |
| Macrocells | β | 160 |
| Logic Array Blocks | β | 4 |
| Usable Gates | β | 3,200 |
| User I/O Pins | β | 64 |
| Pin-to-Pin Delay (tPD) | β | 20 ns |
| Supply Voltage (VCC) | β | 5.0 V |
| Operating Temperature (Commercial) | β | 0C to +70C |
| Programming Interface | β | IEEE 1149.1 JTAG (ISP) |
| In-System Programmable | β | Yes (5.0-V ISP) |
| Package | β | PLCC-84 (windowed ceramic carrier not applicable - plastic) |
| Technology | β | CMOS EEPROM |
| Architecture | β | Second-generation MAX |
| Global Clock Inputs | β | 4 |
| Logic Element Type | β | EEPROM-based macrocell |