EPM7160ELC84-12 vs EPM7160ELC84-20 Vergleich
Detaillierter Direktvergleich von EPM7160ELC84-12 von Altera und EPM7160ELC84-20 von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Altera
EPM7160ELC84-12 - MAX 7000 CPLD, 160 Macrocells, 12ns | Altera
EPM7160ELC84-12 ⚠ Letzte Bestellmöglichkeit
Spezifikationsvergleich
| Parameter | EPM7160ELC84-12 | EPM7160ELC84-20 |
|---|---|---|
| Marke | Altera | Intel |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Letzte Kaufgelegenheit | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $11,10 | $16,95 |
| Manufacturer | Altera (Intel PSG) | — |
| Series | MAX 7000 (MAX 7000E) | — |
| Programmable Type | EE PLD (EEPROM) | — |
| Number of Macrocells | 160 | — |
| Number of Logic Array Blocks (LABs) | 4 | — |
| Number of Usable Gates | 3,200 | — |
| Number of I/O (max) | 68 | — |
| Number of I/O (per package) | 64 | — |
| Propagation Delay tpd(1) max | 12 ns | — |
| Counter Frequency (max) | 90.9 MHz | — |
| Voltage Supply - Internal | 4.75 V to 5.25 V (5 V nominal) | — |
| Betriebstemperatur | 0C to +70C (commercial) | — |
| Gehäuse / Bauform | 84-LCC (J-Lead) | — |
| Supplier Device Package | 84-PLCC (29.31 x 29.31 mm) | — |
| Montageart | Surface Mount | Surface Mount (PLCC socket compatible) |
| In-System Programmability | Yes (IEEE 1149.1 JTAG) | — |
| RoHS-Status | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS compliance per specific part marking] |
| Family | — | MAX 7000 |
| Macrocells | — | 160 |
| Logic Array Blocks | — | 4 |
| Usable Gates | — | 3,200 |
| User I/O Pins | — | 64 |
| Pin-to-Pin Delay (tPD) | — | 20 ns |
| Supply Voltage (VCC) | — | 5.0 V |
| Operating Temperature (Commercial) | — | 0C to +70C |
| Programming Interface | — | IEEE 1149.1 JTAG (ISP) |
| In-System Programmable | — | Yes (5.0-V ISP) |
| Gehäuse | — | PLCC-84 (windowed ceramic carrier not applicable - plastic) |
| Technology | — | CMOS EEPROM |
| Architecture | — | Second-generation MAX |
| Global Clock Inputs | — | 4 |
| Logic Element Type | — | EEPROM-based macrocell |