EPM7160ELC84-12 - MAX 7000 CPLD, 160 Macrocells, 12ns | Altera
MPN: EPM7160ELC84-12 β Last Time Buy| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $18.5 | $18.50 |
| 10 | $16.2 | $162.00 |
| 100 | $13.95 | $1,395.00 |
| 250 | $12.4 | $3,100.00 |
| 500 | $11.1 | $5,550.00 |
Drop-in alternatives for EPM7160ELC84-12 β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
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EPM7160ELC84-15
β Drop-Inβ In Stock
$5.95 / Unit
View Datasheet βEPM7160ELC84-20
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$16.95 / Unit
View Datasheet βEPM7160ELC84-25
β Drop-Inπ Reference alternative (not in catalog)
EPM7160ELI84-15
β Drop-Inπ Reference alternative (not in catalog)
EPM7160ELI84-20
β Drop-Inβ In Stock
$11.1 / Unit
View Datasheet βEPM7160ELC84-12 Maximum Ratings & Electrical Characteristics
| Manufacturer | Altera (Intel PSG) |
| Series | MAX 7000 (MAX 7000E) |
| Programmable Type | EE PLD (EEPROM) |
| Number of Macrocells | 160 |
| Number of Logic Array Blocks (LABs) | 4 |
| Number of Usable Gates | 3,200 |
| Number of I/O (max) | 68 |
| Number of I/O (per package) | 64 |
| Propagation Delay tpd(1) max | 12 ns |
| Counter Frequency (max) | 90.9 MHz |
| Voltage Supply - Internal | 4.75 V to 5.25 V (5 V nominal) |
| Operating Temperature | 0C to +70C (commercial) |
| Package / Case | 84-LCC (J-Lead) |
| Supplier Device Package | 84-PLCC (29.31 x 29.31 mm) |
| Mounting Type | Surface Mount |
| In-System Programmability | Yes (IEEE 1149.1 JTAG) |
EPM7160ELC84-12 Pin Configuration
| Pin 1 | I/O β User I/O (function defined by design) |
| Pin 2 | I/O β User I/O (function defined by design) |
| Pin 3 | I/O β User I/O (function defined by design) |
| Pin 4 | I/O β User I/O (function defined by design) |
| Pin 5 | I/O β User I/O (function defined by design) |
| Pin 6 | I/O β User I/O (function defined by design) |
| Pin 7 | I/O β User I/O (function defined by design) |
| Pin 8 | I/O β User I/O (function defined by design) |
| Pin 9 | I/O β User I/O (function defined by design) |
| Pin 10 | I/O β User I/O (function defined by design) |
| Pin 11 | VCC β 5 V supply |
| Pin 12 | I/O β User I/O (function defined by design) |
| Pin 13 | I/O β User I/O (function defined by design) |
| Pin 14 | I/O β User I/O (function defined by design) |
| Pin 15 | I/O β User I/O (function defined by design) |
| Pin 16 | I/O β User I/O (function defined by design) |
| Pin 17 | I/O β User I/O (function defined by design) |
| Pin 18 | I/O β User I/O (function defined by design) |
| Pin 19 | I/O β User I/O (function defined by design) |
| Pin 20 | I/O β User I/O (function defined by design) |
| Pin 21 | GND β Ground |
| Pin 22 | I/O β User I/O (function defined by design) |
| Pin 23 | I/O β User I/O (function defined by design) |
| Pin 24 | I/O β User I/O (function defined by design) |
| Pin 25 | I/O β User I/O (function defined by design) |
| Pin 26 | I/O β User I/O (function defined by design) |
| Pin 27 | I/O β User I/O (function defined by design) |
| Pin 28 | I/O β User I/O (function defined by design) |
| Pin 29 | I/O β User I/O (function defined by design) |
| Pin 30 | I/O β User I/O (function defined by design) |
| Pin 31 | I/O β User I/O (function defined by design) |
| Pin 32 | I/O β User I/O (function defined by design) |
| Pin 33 | VCC β 5 V supply |
| Pin 34 | I/O β User I/O (function defined by design) |
| Pin 35 | I/O β User I/O (function defined by design) |
| Pin 36 | I/O β User I/O (function defined by design) |
| Pin 37 | I/O β User I/O (function defined by design) |
| Pin 38 | I/O β User I/O (function defined by design) |
| Pin 39 | I/O β User I/O (function defined by design) |
| Pin 40 | I/O β User I/O (function defined by design) |
| Pin 41 | I/O β User I/O (function defined by design) |
| Pin 42 | GND β Ground |
| Pin 43 | GCLK1 β Global clock input 1 (dedicated) |
| Pin 44 | OE1 β Global output enable 1 (dedicated) |
| Pin 45 | TDI β JTAG test data input |
| Pin 46 | TMS β JTAG test mode select |
| Pin 47 | TCK β JTAG test clock |
| Pin 48 | I/O β User I/O (function defined by design) |
| Pin 49 | I/O β User I/O (function defined by design) |
| Pin 50 | I/O β User I/O (function defined by design) |
| Pin 51 | I/O β User I/O (function defined by design) |
| Pin 52 | I/O β User I/O (function defined by design) |
| Pin 53 | I/O β User I/O (function defined by design) |
| Pin 54 | I/O β User I/O (function defined by design) |
| Pin 55 | I/O β User I/O (function defined by design) |
| Pin 56 | I/O β User I/O (function defined by design) |
| Pin 57 | I/O β User I/O (function defined by design) |
| Pin 58 | I/O β User I/O (function defined by design) |
| Pin 59 | I/O β User I/O (function defined by design) |
| Pin 60 | VCC β 5 V supply |
| Pin 61 | I/O β User I/O (function defined by design) |
| Pin 62 | I/O β User I/O (function defined by design) |
| Pin 63 | I/O β User I/O (function defined by design) |
| Pin 64 | I/O β User I/O (function defined by design) |
| Pin 65 | I/O β User I/O (function defined by design) |
| Pin 66 | I/O β User I/O (function defined by design) |
| Pin 67 | I/O β User I/O (function defined by design) |
| Pin 68 | I/O β User I/O (function defined by design) |
| Pin 69 | GCLK2 β Global clock input 2 (dedicated) |
| Pin 70 | OE2 β Global output enable 2 (dedicated) |
| Pin 71 | TDO β JTAG test data output |
| Pin 72 | I/O β User I/O (function defined by design) |
| Pin 73 | I/O β User I/O (function defined by design) |
| Pin 74 | I/O β User I/O (function defined by design) |
| Pin 75 | I/O β User I/O (function defined by design) |
| Pin 76 | I/O β User I/O (function defined by design) |
| Pin 77 | I/O β User I/O (function defined by design) |
| Pin 78 | I/O β User I/O (function defined by design) |
| Pin 79 | I/O β User I/O (function defined by design) |
| Pin 80 | I/O β User I/O (function defined by design) |
| Pin 81 | I/O β User I/O (function defined by design) |
| Pin 82 | I/O β User I/O (function defined by design) |
| Pin 83 | I/O β User I/O (function defined by design) |
| Pin 84 | GND β Ground |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM7160ELC84-12 is suitable for 6 applications: Microprocessor Bus Decoding and Address Mapping, Industrial Control and Factory Automation Glue Logic, Legacy Replacement of Discrete 74-Series TTL/CMOS Gates, Telecommunication Line-Card Control Logic, State-Machine and Sequencer Designs, LED Display and Sign Multiplexing.
Microprocessor Bus Decoding and Address Mapping
The EPM7160ELC84-12 is well suited to microprocessor bus decoding because its 160 macrocells and 64 user I/Os can absorb an entire 8/16/32-bit address decode tree plus chip-select glue, replacing dozens of 74-series TTL gates on a single 5 V device. Its 12 ns pin-to-pin delay keeps the decoded chip-select ahead of typical 80C186/68k/8086 access times (typically 30-60 ns), and its deterministic, instant-on EEPROM-based configuration means there is no firmware boot delay on power-up. Designers typically instantiate one LAB per major decode region (e.g. boot ROM, SRAM, peripheral block) and use the global clock pins for synchronous qualifier logic. Because the device runs from a single 5 V rail with no separate core voltage, it is a drop-in upgrade from legacy bipolar or CMOS PLDs without disturbing the existing power tree.
Recommended
Industrial Control and Factory Automation Glue Logic
In industrial 24V/5V control systems, the EPM7160ELC84-12 serves as the central glue-logic device that interfaces sensor inputs, opto-isolated control lines, and 5 V peripheral ICs with the host microcontroller. Its 64 user I/Os handle multiple input debouncing, latching, and output muxing channels in parallel, while its 12 ns tpd and 90.9 MHz counter rate support encoder quadrature decoding or PWM-timing peripherals on-chip. Commercial temperature (0C to +70C) is acceptable for cabinet-mounted equipment; the EPM7160ELI84-20 industrial variant is recommended when the device sits outside the enclosure. The 84-pin PLCC package is robust to vibration when socketed, and JTAG ISP allows field firmware updates for I/O protocol changes. Designers should budget I/O count carefully because MAX 7000 I/Os are 5 V TTL only - level shifting is required for 3.3 V peripherals.
Recommended
Legacy Replacement of Discrete 74-Series TTL/CMOS Gates
The EPM7160ELC84-12 is frequently used as a board-level consolidation replacement for clusters of 74LS, 74HC, and 74F-series glue-logic ICs, replacing up to 40-60 small-scale packages with a single PLCC-84 CPLD. This reduces PCB area, power consumption (a single 5 V CPLD vs. dozens of separate ICs each with their own quiescent draw), and BOM cost on legacy designs being refreshed. Designers port the schematic one-for-one into Altera MAX+PLUS II HDL (AHDL) or VHDL, run a quick fit, and verify timing with the simulator - the deterministic MAX 7000E timing model makes this fast and predictable. The 12 ns grade is recommended for designs that originally used 74F or 74AS logic; designs originally on 74LS or 74HC have generous timing margin and can use the cheaper -15 or -20 grade. JTAG ISP lets the board be reworked without desoldering.
Recommended
Telecommunication Line-Card Control Logic
In T1/E1, ISDN, and legacy PSTN line-card designs, the EPM7160ELC84-12 provides deterministic, near-zero standby power for supervisory control logic such as relay drivers, line-feed control, ring-trip detection, and codec interface glue. The single 5 V supply, 64 I/Os, and JTAG ISP are well matched to the 5 V backplane power rails typical in telecom hardware. Its 12 ns tpd supports HDLC or voice-band framing functions at standard 1.544/2.048 MHz rates with margin to spare. The MAX 7000 family was a long-standing choice in this segment because of its 5 V tolerance, in-system reprogrammability for protocol upgrades, and wide operating-temperature grade (industrial variant for outdoor cabinets). Engineers should verify the 5 V I/O tolerance against newer 3.3 V codec devices and add bus switches or level shifters if mixing voltage domains.
Recommended
State-Machine and Sequencer Designs
For power-supply sequencing, motor-control state machines, and test-instrument sequencers, the EPM7160ELC84-12 delivers predictable, deterministic timing that fits the problem perfectly. The 160 macrocells can encode a 16-state FSM with output-decoded actions plus parallel register banks for status flags, and the four dedicated global clocks drive state-machine clocks, capture clocks, and PWM carriers independently. Because the device is EEPROM-based, the state-machine design powers up already configured - critical for safety logic where the supervisor must come out of reset in a known state, not waiting for SRAM-based configuration. The 12 ns pin-to-pin delay lets the CPLD resolve state-machine outputs within one fast-clock period, supporting sequencers with up to 90 MHz internal state-update rates. Designers should document state encodings and unused-pin states explicitly because unused macrocells still consume a small standby current.
Recommended
LED Display and Sign Multiplexing
Large LED matrix signs and 7-segment display panels often use a CPLD such as the EPM7160ELC84-12 to drive row/column multiplexers, generate blanking intervals, and handle brightness modulation. Its 64 user I/Os can directly drive a 16x32 single-color matrix or a 7-segment display cluster, and the 90.9 MHz counter rate supports high-refresh-rate PWM dimming without flicker. The 5 V TTL outputs match the drive requirement of most LED driver ICs, eliminating external buffers. Because each design is unique, designers use MAX+PLUS II to specify pin assignments manually, keeping high-frequency switching outputs away from sensitive analog lines on the board. For RGB panels, the 64-I/O budget is often tight - consider migrating to a larger MAX 7000 device (EPM7256S) or a small FPGA for color-depth expansion.
Recommended
Recommended Products Summary
Engineering reference data for EPM7160ELC84-12 β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM7160ELC84-15 | EPM7160ELC84-20 | EPM7160ELC84-25 | EPM7160ELI84-15 | EPM7160ELI84-20 |
|---|---|---|---|---|---|---|
| Brand | Altera (Intel PSG) | Altera (Intel PSG) | Altera (Intel PSG) | Altera (Intel PSG) | Altera (Intel PSG) | Altera (Intel PSG) |
| Package | 84-PLCC (J-Lead) - same | 84-PLCC (J-Lead) | 84-PLCC (J-Lead) | 84-PLCC (J-Lead) | 84-PLCC (J-Lead) | 84-PLCC (J-Lead) |
| Propagation Delay tpd(1) max | 12 ns | 15 ns (+25%) | 20 ns (+67%) | 25 ns (+108%) | 15 ns (+25%) | 20 ns (+67%) |
| Counter Frequency (max) | 90.9 MHz | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] |
| Macrocells | 160 | 160 | 160 | 160 | 160 | 160 |
| Logic Array Blocks | 4 | 4 | 4 | 4 | 4 | 4 |
| User I/O (this package) | 64 | 64 | 64 | 64 | 64 | 64 |
| Usable Gates | 3,200 | 3,200 | 3,200 | 3,200 | 3,200 | 3,200 |
| Operating Temperature | 0C to +70C (commercial) | 0C to +70C (commercial) | 0C to +70C (commercial) | 0C to +70C (commercial) | -40C to +85C (industrial) | -40C to +85C (industrial) |
| Supply Voltage | 4.75 V to 5.25 V | 4.75 V to 5.25 V | 4.75 V to 5.25 V | 4.75 V to 5.25 V | 4.75 V to 5.25 V | 4.75 V to 5.25 V |
| In-System Programmability | Yes (JTAG IEEE 1149.1) | Yes (JTAG) | Yes (JTAG) | Yes (JTAG) | Yes (JTAG) | Yes (JTAG) |
Key Differentiators
- Highest speed grade in MAX 7000E 84-pin PLCC family (vs EPM7160ELC84-15)
- Commercial temperature grade optimized for controlled-environment deployments (vs EPM7160ELI84-20)
- 160 macrocells and 64 I/Os balance density vs cost in the MAX 7000E line (vs EPM7128ELC84-12 (128 macrocells, same PLCC-84))
Design Notes
The 84-pin PLCC package is NOT pin-compatible with any QFP/TQFP package in the same MAX 7000 family; migrating between packages requires PCB redesign. Verify that PCB layout reserves clearance for the J-lead footprint (recommended land pattern per IPC-7351 PLCC-84) and consider a PLCC-84 socket for prototype rework. JTAG pins (TDI/TDO/TMS/TCK on pins 45-47 and 71) must be brought out to a header or test pad - burying them prevents in-system programming and field firmware upgrades, which is the primary benefit of the MAX 7000 family over legacy PROMs.
The MAX 7000E ICC quiescent current is approximately 5-15 mA standby; dynamic current scales with the number of toggling outputs and the toggle frequency. Estimate: I_dynamic ~= N_outputs * C_load * VCC * f_toggle. With all 64 I/Os at 10 MHz into 50 pF loads, expect an additional ~80 mA on top of standby. Place 0.1 uF ceramic decoupling caps close to every VCC pin (4 VCC pins: 11, 33, 60 plus a fourth; cross-reference the package pinout) and a single 10 uF tantalum/ceramic bulk cap at the supply entry.
Keep JTAG chain routing short and isolated from high-frequency switching signals. The TCK pin is particularly sensitive - long traces pick up noise and cause JTAG programming failures. If the design includes other JTAG devices on the same chain (e.g. microcontrollers, FPGAs), order the chain so that the CPLD is bypass-friendly and verify the chain with Altera's JTAG chain debugger tool before depending on field upgrades. Reserve unused I/Os as outputs tied low (not inputs floating) to minimize standby current.
MAX 7000E I/O buffers are 5 V TTL-compatible with edge rates around 1-2 ns. For bus speeds above 25 MHz, add 33 ohm series-termination resistors on heavily-loaded outputs to dampen ringing. Avoid routing outputs adjacent to analog sections of the board; the CPLD is not a quiet part. For designs that mix 3.3 V peripherals, add bus switches (e.g. 74CBTLV3253) or level-shifters - the MAX 7000 outputs are not 3.3 V-tolerant on the inputs.
Compliance Information
RoHS/REACH/lead-free status not stated in the verified web data for the EPM7160ELC84-12. The MAX 7000 family includes both lead and lead-free variants - confirm the specific finish code with the distributor before ordering for RoHS-compliant assemblies. AEC-Q100 not applicable - this is a commercial-grade logic device, not an automotive-qualified part.
