EPM7160ELC84-12 vs EPM7160SLC84-15 Comparison

Detailed side-by-side comparison of EPM7160ELC84-12 by Altera and EPM7160SLC84-15 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Altera
EPM7160ELC84-12 EPM7160ELC84-12 - MAX 7000 CPLD, 160 Macrocells, 12ns | Altera

EPM7160ELC84-12 - MAX 7000 CPLD, 160 Macrocells, 12ns | Altera

EPM7160ELC84-12 ⚠ Last Time Buy

Specification Comparison

Parameter EPM7160ELC84-12 EPM7160SLC84-15
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Last Time Buy Obsolete
Manufacturer Altera (Intel PSG) —
Series MAX 7000 (MAX 7000E) —
Programmable Type EE PLD (EEPROM) —
Number of Macrocells 160 —
Number of Logic Array Blocks (LABs) 4 —
Number of Usable Gates 3,200 —
Number of I/O (max) 68 —
Number of I/O (per package) 64 —
Propagation Delay tpd(1) max 12 ns —
Counter Frequency (max) 90.9 MHz —
Voltage Supply - Internal 4.75 V to 5.25 V (5 V nominal) —
Operating Temperature 0C to +70C (commercial) 0 C to 70 C
Package / Case 84-LCC (J-Lead) —
Supplier Device Package 84-PLCC (29.31 x 29.31 mm) —
Mounting Type Surface Mount Surface Mount (PLCC socket or direct solder)
In-System Programmability Yes (IEEE 1149.1 JTAG) —
RoHS Status [DATA_NEEDED: RoHS status] Not RoHS compliant (contains lead, SnPb finish typical)
Family — MAX 7000
Macrocells — 160
Usable Gates — 3,200
Maximum Propagation Delay — 15 ns
Maximum User I/O Pins — 64
Supply Voltage (VCCINT/VCIO) — 4.75 V to 5.25 V (5 V nominal)
I/O Logic Level — Configurable 3.3 V or 5 V
Technology — CMOS, EEPROM configuration
Package Type — PLCC-84 (PQCC84, JEDEC S-PQCC-J84)
Terminal Pitch — 1.270 mm
Programming Interface — JTAG (IEEE 1149.1) in-system programmable
Lifecycle — Obsolete / last-time-buy (per Altera/Intel PDN)

Datasheets & Resources

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