EPM7160SLC84-15 - MAX 7000 CPLD, 160 Macrocells, 15ns | Altera
MPN: EPM7160SLC84-15 ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $18.5 | $18.50 |
| 10 | $16.4 | $164.00 |
| 100 | $14.1 | $1,410.00 |
| 500 | $12.25 | $6,125.00 |
| 1,000 | $10.8 | $10,800.00 |
Drop-in alternatives for EPM7160SLC84-15 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EPM7160SLC84-10
✅ Drop-In✓ In Stock
$35.77 / Unit
View Datasheet →EPM7160SLC84-10N
✅ Drop-In✓ In Stock
$9.85 / Unit
View Datasheet →EPM7160ELC84-15
✅ Drop-In✓ In Stock
$5.95 / Unit
View Datasheet →EPM7160ELC84-12
✅ Drop-In✓ In Stock
$11.1 / Unit
View Datasheet →EPM7160ELI84-20
✅ Drop-In✓ In Stock
$11.1 / Unit
View Datasheet →EPM7128SLC84-15
✅ Drop-In✓ In Stock
$10.4 / Unit
View Datasheet →EPM7160SLC84-15 Maximum Ratings & Electrical Characteristics
| Family | MAX 7000 |
| Macrocells | 160 |
| Usable Gates | 3,200 |
| Maximum Propagation Delay | 15 ns |
| Maximum User I/O Pins | 64 |
| Supply Voltage (VCCINT/VCIO) | 4.75 V to 5.25 V (5 V nominal) |
| I/O Logic Level | Configurable 3.3 V or 5 V |
| Technology | CMOS, EEPROM configuration |
| Package Type | PLCC-84 (PQCC84, JEDEC S-PQCC-J84) |
| Terminal Pitch | 1.270 mm |
| Mounting Type | Surface Mount (PLCC socket or direct solder) |
| Operating Temperature | 0 C to 70 C |
| Programming Interface | JTAG (IEEE 1149.1) in-system programmable |
| RoHS Status | Not RoHS compliant (contains lead, SnPb finish typical) |
| Lifecycle | Obsolete / last-time-buy (per Altera/Intel PDN) |
EPM7160SLC84-15 Pin Configuration
| Pin 1 | I/O — User I/O pin |
| Pin 2 | I/O — User I/O pin |
| Pin 3 | I/O — User I/O pin |
| Pin 4 | I/O — User I/O pin |
| Pin 5 | I/O — User I/O pin |
| Pin 6 | I/O — User I/O pin |
| Pin 7 | I/O — User I/O pin |
| Pin 8 | I/O — User I/O pin |
| Pin 9 | I/O — User I/O pin |
| Pin 10 | I/O — User I/O pin |
| Pin 11 | GND — Ground |
| Pin 12 | I/O — User I/O pin |
| Pin 13 | I/O — User I/O pin |
| Pin 14 | I/O — User I/O pin |
| Pin 15 | I/O — User I/O pin |
| Pin 16 | I/O — User I/O pin |
| Pin 17 | I/O — User I/O pin |
| Pin 18 | I/O — User I/O pin |
| Pin 19 | I/O — User I/O pin |
| Pin 20 | I/O — User I/O pin |
| Pin 21 | I/O — User I/O pin |
| Pin 22 | GND — Ground |
| Pin 23 | I/O — User I/O pin |
| Pin 24 | I/O — User I/O pin |
| Pin 25 | I/O — User I/O pin |
| Pin 26 | I/O — User I/O pin |
| Pin 27 | I/O — User I/O pin |
| Pin 28 | I/O — User I/O pin |
| Pin 29 | I/O — User I/O pin |
| Pin 30 | I/O — User I/O pin |
| Pin 31 | I/O — User I/O pin |
| Pin 32 | I/O — User I/O pin |
| Pin 33 | GND — Ground |
| Pin 34 | I/O — User I/O pin |
| Pin 35 | I/O — User I/O pin |
| Pin 36 | I/O — User I/O pin |
| Pin 37 | I/O — User I/O pin |
| Pin 38 | I/O — User I/O pin |
| Pin 39 | I/O — User I/O pin |
| Pin 40 | I/O — User I/O pin |
| Pin 41 | I/O — User I/O pin |
| Pin 42 | I/O — User I/O pin |
| Pin 43 | GND — Ground |
| Pin 44 | I/O — User I/O pin |
| Pin 45 | I/O — User I/O pin |
| Pin 46 | I/O — User I/O pin |
| Pin 47 | I/O — User I/O pin |
| Pin 48 | I/O — User I/O pin |
| Pin 49 | I/O — User I/O pin |
| Pin 50 | I/O — User I/O pin |
| Pin 51 | I/O — User I/O pin |
| Pin 52 | I/O — User I/O pin |
| Pin 53 | I/O — User I/O pin |
| Pin 54 | GND — Ground |
| Pin 55 | I/O — User I/O pin |
| Pin 56 | I/O — User I/O pin |
| Pin 57 | I/O — User I/O pin |
| Pin 58 | I/O — User I/O pin |
| Pin 59 | I/O — User I/O pin |
| Pin 60 | I/O — User I/O pin |
| Pin 61 | I/O — User I/O pin |
| Pin 62 | I/O — User I/O pin |
| Pin 63 | I/O — User I/O pin |
| Pin 64 | I/O — User I/O pin |
| Pin 65 | GND — Ground |
| Pin 66 | I/O — User I/O pin |
| Pin 67 | I/O — User I/O pin |
| Pin 68 | I/O — User I/O pin |
| Pin 69 | I/O — User I/O pin |
| Pin 70 | I/O — User I/O pin |
| Pin 71 | I/O — User I/O pin |
| Pin 72 | I/O — User I/O pin |
| Pin 73 | I/O — User I/O pin |
| Pin 74 | I/O — User I/O pin |
| Pin 75 | I/O — User I/O pin |
| Pin 76 | GND — Ground |
| Pin 77 | TCK — JTAG test clock (IEEE 1149.1) |
| Pin 78 | TMS — JTAG test mode select |
| Pin 79 | TDI — JTAG test data in |
| Pin 80 | TDO — JTAG test data out |
| Pin 81 | ENABLE — Device enable (low to program) |
| Pin 82 | GCLK — Global clock input |
| Pin 83 | OE1 — Output enable 1 (global) |
| Pin 84 | VCC — +5 V supply (VCCINT and VCIO) |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM7160SLC84-15 is suitable for 6 applications: Industrial Control Glue Logic, Telecommunications Infrastructure Bus Interfaces, Legacy Microprocessor Address Decoding, I/O Expansion and Register Replacement, Consumer Electronics Peripheral Controllers, Prototyping and Education Platforms.
Industrial Control Glue Logic
The EPM7160SLC84-15 is well suited for industrial control glue-logic applications because its 160 macrocells and 3,200 usable gates provide ample capacity for address decoding, bus arbitration, and discrete state-machine replacement while the 15 ns pin-to-pin delay meets typical PLC scan-cycle timing budgets. Configurable 5 V or 3.3 V I/O allows the CPLD to interface directly with legacy 5 V peripheral buses (e.g., ISA, PC/104, HCTL) without level shifters, and the JTAG ISP interface lets field-service technicians update logic without removing the board.
Recommended
Telecommunications Infrastructure Bus Interfaces
In telecom backplane and line-card designs, the EPM7160SLC84-15 provides deterministic 15 ns timing for address decoding, chip-select generation, and protocol glue between processors, ASICs, and bus switches. Its 64 user I/O pins comfortably handle TDM bus multiplexing and HDLC channel routing, and the non-volatile EEPROM configuration eliminates the boot-time delay of SRAM-based FPGAs. The PLCC-84 footprint suits legacy CompactPCI and VMEbus cards where board re-spin cost is high.
Recommended
Legacy Microprocessor Address Decoding
The EPM7160SLC84-15 is a classic choice for replacing 74-series TTL/CMOS address decoding trees around legacy processors such as the 8086, 68000, Z80, or 8051 family. Its 15 ns propagation delay fits comfortably within typical 8 MHz to 33 MHz memory-access windows, and the 64 user I/O pins support multiple chip-select outputs, wait-state generators, and interrupt controllers in a single device. The PLCC-84 socketed package simplifies prototyping on wire-wrap or through-hole evaluation boards.
Recommended
I/O Expansion and Register Replacement
Designers use the EPM7160SLC84-15 to consolidate discrete 74HC573, 74HC574, 74HC245, and 74HC138 functions into a single programmable device, reducing PCB area and BOM count. Each macrocell provides a flip-flop plus tri-state I/O control, so the CPLD can act as a multi-port register file, parallel FIFO, or generic latch array. With 64 I/O pins, the -15 grade can replace up to sixteen 8-bit buffer chips in a typical peripheral interface design.
Recommended
Consumer Electronics Peripheral Controllers
In consumer appliances such as set-top boxes, DVD players, and washing-machine controllers, the EPM7160SLC84-15 replaces dozens of discrete logic gates with a single non-volatile programmable device, simplifying firmware updates during production runs. Its commercial 0 C to 70 C temperature range covers indoor consumer environments, and the 5 V tolerant I/O supports direct drive of relay coils and LED indicator arrays.
Recommended
Prototyping and Education Platforms
Universities and design labs use the EPM7160SLC84-15 in digital-logic courses because its PLCC-84 socketed package tolerates repeated insertion cycles, the JTAG ISP interface avoids external programmers, and the 160-macrocell capacity is large enough for instructional designs (traffic-light controllers, ALUs, UARTs) without overwhelming students. The Altera MAX+PLUS II student edition is freely available and supports the MAX 7000 family.
Recommended
Recommended Products Summary
Engineering reference data for EPM7160SLC84-15 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM7160SLC84-10 | EPM7160SLC84-10N | EPM7160ELC84-15 | EPM7160ELC84-12 | EPM7160ELI84-20 | EPM7128SLC84-15 |
|---|---|---|---|---|---|---|---|
| Brand | Altera | Altera | Altera | Altera | Altera | Altera | Altera |
| Package | PLCC-84 (PQCC84) | PLCC-84 (PQCC84) - same | PLCC-84 (PQCC84) - same | PLCC-84 (PQCC84) - same | PLCC-84 (PQCC84) - same | PLCC-84 (PQCC84) - same | PLCC-84 (PQCC84) - same |
| Macrocells | 160 | 160 | 160 | 160 | 160 | 160 | 128 |
| Propagation Delay | 15 ns | 10 ns (faster) | 10 ns (faster) | 15 ns | 12 ns (faster) | 20 ns (slower) | 15 ns |
| Sub-family | MAX 7000 | MAX 7000 | MAX 7000 | MAX 7000E (Enhanced) | MAX 7000E (Enhanced) | MAX 7000E (Enhanced) | MAX 7000 |
| Operating Temperature | 0 C to 70 C (Commercial) | 0 C to 70 C | -40 C to +85 C (Industrial) | 0 C to 70 C | 0 C to 70 C | -40 C to +85 C (Industrial) | 0 C to 70 C |
| Supply Voltage | 4.75 V to 5.25 V | 4.75 V to 5.25 V | 4.75 V to 5.25 V | 4.75 V to 5.25 V | 4.75 V to 5.25 V | 4.75 V to 5.25 V | 4.75 V to 5.25 V |
| User I/O Pins | 64 | 64 | 64 | 64 | 64 | 64 | 64 |
| Programming Interface | JTAG (IEEE 1149.1) ISP | JTAG ISP | JTAG ISP | JTAG ISP (Enhanced) | JTAG ISP (Enhanced) | JTAG ISP (Enhanced) | JTAG ISP |
Key Differentiators
- Classic MAX 7000 architecture with proven field reliability (vs EPM7160ELC84-15)
- 15 ns speed grade provides ample timing margin for legacy microprocessors (vs EPM7160SLC84-10)
- Commercial 0-70 C temperature range suits indoor/office equipment (vs EPM7160ELI84-20)
Design Notes
Decouple the EPM7160SLC84-15 with at least one 0.1 uF ceramic capacitor within 1 cm of every VCC pin (pin 84 plus any additional VCC pins) and one bulk 10 uF tantalum or aluminum electrolytic capacitor near the package. The MAX 7000 internal core draws up to 200 mA during programming pulses, so a poor decoupling network will cause VCC droop and JTAG programming failures. Estimated: at 5 V with all I/O switching at 25 MHz, average ICC is approximately 150 mA per the MAX 7000 datasheet ICC vs frequency curves.
Place the JTAG header (TCK/TMS/TDI/TDO/ENABLE/GND) within 5 cm of the device to preserve signal integrity during in-system programming. Use a 2.54 mm 2x5 or 1x6 pin header following the Altera ByteBlaster pinout. Keep the JTAG traces away from high-speed switching signals and clock edges; add a 10 kohm pull-up on TDI and TMS to prevent spurious JTAG state transitions during board power-up.
The EPM7160SLC84-15 is NOT RoHS compliant - the PLCC-84 package uses a tin-lead (SnPb) solder finish, and attempting to reflow it at lead-free peak temperatures (245 C) will damage the plastic body. For new RoHS designs, choose the EPM7160EQC160-12 (EQFP-160) or migrate to a MAX II / MAX V CPLD. Also note that the ENABLE pin must be held high during normal operation; tying it to GND will place the device in programming mode and all I/O will be tri-stated.
Compliance Information
PLCC-84 package uses tin-lead (SnPb) solder finish per MAX 7000 family datasheet. Not AEC-Q100 qualified (commercial grade only). Lifecycle is obsolete/last-time-buy per Altera/Intel PDN for the MAX 7000 classic series.
