EPM7160SLC84-10N vs EPM7160SLC84-15 Comparison
Detailed side-by-side comparison of EPM7160SLC84-10N by Intel and EPM7160SLC84-15 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Intel
EPM7160SLC84-10N
EPM7160SLC84-10N - MAX 7000S CPLD 160 Macrocells 84-PLCC | Intel
EPM7160SLC84-10N ObsoleteAltera
EPM7160SLC84-15
EPM7160SLC84-15 - MAX 7000 CPLD, 160 Macrocells, 15ns | Altera
EPM7160SLC84-15 ObsoleteSpecification Comparison
| Parameter | EPM7160SLC84-10N | EPM7160SLC84-15 |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $9.85 | $10.80 |
| Family | MAX 7000S | MAX 7000 |
| Logic Elements / Macrocells | 160 macrocells | β |
| Usable Gates | 3,200 gates | 3,200 |
| Logic Array Blocks (LABs) | 4 | β |
| User I/O Pins | 64 (also reported as 60 or 36 depending on variant) | β |
| Pin-to-Pin Delay (tPD) | 10 ns | β |
| Counter Speed (fCNT) | up to 175.4 MHz | β |
| Maximum Operating Frequency | 100 MHz | β |
| Supply Voltage - Core (VCC) | 5.0 V | β |
| I/O Supply Voltage (VCCIO) | 3.3 V or 5.0 V | β |
| Configuration Memory | EEPROM (non-volatile) | β |
| In-System Programming | Yes, via IEEE Std. 1149.1 JTAG | β |
| Program / Erase Cycles | 100 minimum | β |
| Data Retention | 20 years minimum | β |
| Package | 84-pin PLCC (J-lead, surface mount) | β |
| Operating Temperature Grade | Commercial (0C to +70C) | β |
| Lead-Free / RoHS | Yes (-N suffix indicates lead-free) | β |
| Mounting Type | Surface Mount | Surface Mount (PLCC socket or direct solder) |
| Macrocells | β | 160 |
| Maximum Propagation Delay | β | 15 ns |
| Maximum User I/O Pins | β | 64 |
| Supply Voltage (VCCINT/VCIO) | β | 4.75 V to 5.25 V (5 V nominal) |
| I/O Logic Level | β | Configurable 3.3 V or 5 V |
| Technology | β | CMOS, EEPROM configuration |
| Package Type | β | PLCC-84 (PQCC84, JEDEC S-PQCC-J84) |
| Terminal Pitch | β | 1.270 mm |
| Operating Temperature | β | 0 C to 70 C |
| Programming Interface | β | JTAG (IEEE 1149.1) in-system programmable |
| RoHS Status | β | Not RoHS compliant (contains lead, SnPb finish typical) |
| Lifecycle | β | Obsolete / last-time-buy (per Altera/Intel PDN) |