EPM7160SLC84-10N - MAX 7000S CPLD 160 Macrocells 84-PLCC | Intel
MPN: EPM7160SLC84-10N β End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $18.5 | $18.50 |
| 10 | $16.2 | $162.00 |
| 100 | $13.75 | $1,375.00 |
| 500 | $11.4 | $5,700.00 |
| 1,000 | $9.85 | $9,850.00 |
Drop-in alternatives for EPM7160SLC84-10N β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
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EPM7160SLC84-10
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View Datasheet βEPM7160SLC84-10N Maximum Ratings & Electrical Characteristics
| Family | MAX 7000S |
| Logic Elements / Macrocells | 160 macrocells |
| Usable Gates | 3,200 gates |
| Logic Array Blocks (LABs) | 4 |
| User I/O Pins | 64 (also reported as 60 or 36 depending on variant) |
| Pin-to-Pin Delay (tPD) | 10 ns |
| Counter Speed (fCNT) | up to 175.4 MHz |
| Maximum Operating Frequency | 100 MHz |
| Supply Voltage - Core (VCC) | 5.0 V |
| I/O Supply Voltage (VCCIO) | 3.3 V or 5.0 V |
| Configuration Memory | EEPROM (non-volatile) |
| In-System Programming | Yes, via IEEE Std. 1149.1 JTAG |
| Program / Erase Cycles | 100 minimum |
| Data Retention | 20 years minimum |
| Package | 84-pin PLCC (J-lead, surface mount) |
| Operating Temperature Grade | Commercial (0C to +70C) |
| Lead-Free / RoHS | Yes (-N suffix indicates lead-free) |
| Mounting Type | Surface Mount |
EPM7160SLC84-10N Pin Configuration
| Pin 1 | I/O β User I/O pin (macrocell input/output) |
| Pin 2 | I/O β User I/O pin |
| Pin 3 | I/O β User I/O pin |
| Pin 4 | I/O β User I/O pin |
| Pin 5 | I/O β User I/O pin |
| Pin 6 | I/O β User I/O pin |
| Pin 7 | I/O β User I/O pin |
| Pin 8 | I/O β User I/O pin |
| Pin 9 | I/O β User I/O pin |
| Pin 10 | I/O β User I/O pin |
| Pin 11 | GND β Ground |
| Pin 12 | I/O β User I/O pin |
| Pin 13 | I/O β User I/O pin |
| Pin 14 | I/O β User I/O pin |
| Pin 15 | I/O β User I/O pin |
| Pin 16 | I/O β User I/O pin |
| Pin 17 | I/O β User I/O pin |
| Pin 18 | I/O β User I/O pin |
| Pin 19 | I/O β User I/O pin |
| Pin 20 | I/O β User I/O pin |
| Pin 21 | VCC β Core 5.0 V supply |
| Pin 22 | I/O β User I/O pin |
| Pin 23 | I/O β User I/O pin |
| Pin 24 | I/O β User I/O pin |
| Pin 25 | I/O β User I/O pin |
| Pin 26 | I/O β User I/O pin |
| Pin 27 | I/O β User I/O pin |
| Pin 28 | I/O β User I/O pin |
| Pin 29 | I/O β User I/O pin |
| Pin 30 | I/O β User I/O pin |
| Pin 31 | GND β Ground |
| Pin 32 | I/O β User I/O pin |
| Pin 33 | I/O β User I/O pin |
| Pin 34 | I/O β User I/O pin |
| Pin 35 | I/O β User I/O pin |
| Pin 36 | I/O β User I/O pin |
| Pin 37 | I/O β User I/O pin |
| Pin 38 | I/O β User I/O pin |
| Pin 39 | I/O β User I/O pin |
| Pin 40 | I/O β User I/O pin |
| Pin 41 | VCC β Core 5.0 V supply |
| Pin 42 | I/O β User I/O pin |
| Pin 43 | I/O β User I/O pin |
| Pin 44 | I/O β User I/O pin |
| Pin 45 | I/O β User I/O pin |
| Pin 46 | I/O β User I/O pin |
| Pin 47 | I/O β User I/O pin |
| Pin 48 | I/O β User I/O pin |
| Pin 49 | I/O β User I/O pin |
| Pin 50 | I/O β User I/O pin |
| Pin 51 | GND β Ground |
| Pin 52 | I/O β User I/O pin |
| Pin 53 | I/O β User I/O pin |
| Pin 54 | I/O β User I/O pin |
| Pin 55 | I/O β User I/O pin |
| Pin 56 | I/O β User I/O pin |
| Pin 57 | I/O β User I/O pin |
| Pin 58 | I/O β User I/O pin |
| Pin 59 | I/O β User I/O pin |
| Pin 60 | I/O β User I/O pin |
| Pin 61 | VCCIO β I/O supply voltage (3.3 V or 5.0 V) |
| Pin 62 | I/O β User I/O pin |
| Pin 63 | I/O β User I/O pin |
| Pin 64 | I/O β User I/O pin |
| Pin 65 | I/O β User I/O pin |
| Pin 66 | I/O β User I/O pin |
| Pin 67 | I/O β User I/O pin |
| Pin 68 | I/O β User I/O pin |
| Pin 69 | I/O β User I/O pin |
| Pin 70 | I/O β User I/O pin |
| Pin 71 | GND β Ground |
| Pin 72 | I/O β User I/O pin |
| Pin 73 | I/O β User I/O pin |
| Pin 74 | I/O β User I/O pin |
| Pin 75 | I/O β User I/O pin |
| Pin 76 | I/O β User I/O pin |
| Pin 77 | I/O β User I/O pin |
| Pin 78 | I/O β User I/O pin |
| Pin 79 | I/O β User I/O pin |
| Pin 80 | I/O β User I/O pin |
| Pin 81 | VCC β Core 5.0 V supply |
| Pin 82 | TDI β JTAG Test Data In |
| Pin 83 | TMS β JTAG Test Mode Select |
| Pin 84 | TCK β JTAG Test Clock |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM7160SLC84-10N is suitable for 6 applications: Industrial Control Glue Logic, Telecommunications Address Decoding, Peripheral Interfacing and Bus Bridging, State Machine Control Logic, Legacy System Maintenance and Re-Design, Test Equipment and Instrumentation.
Industrial Control Glue Logic
The EPM7160SLC84-10N is widely deployed in factory automation PLCs and motor controllers where deterministic 10 ns pin-to-pin timing and instant-on non-volatile configuration eliminate boot-time delays. With 160 macrocells and 64 I/O pins, it can replace 5-8 discrete PAL/GAL devices plus their supporting latches, reducing board area and BOM cost. The 5V core supply with 3.3V/5V-tolerant I/O lets it interface directly to legacy 5V optocouplers and 3.3V MCUs in mixed-voltage control boards, while the commercial 0-70C temperature grade covers most factory-floor environments. The MAX 7000S JTAG ISP capability enables field firmware updates without removing the device from the PCB.
Recommended
Telecommunications Address Decoding
Telecom backplane designs use the EPM7160SLC84-10N for address decoding, chip-select generation, and bus arbitration across multi-board systems. The device's 160 macrocells can decode a full 24-32 bit address range with several chip-select outputs, while 10 ns tPD ensures it does not bottleneck synchronous bus cycles. The 84-pin PLCC package provides sufficient I/O for bus control signals including /CS, /OE, /RD, /WR, and interrupt acknowledge lines. JTAG ISP allows last-minute board reconfiguration when address maps change between hardware revisions, and the EEPROM-based configuration guarantees deterministic behavior at power-up without external boot ROM.
Recommended
Peripheral Interfacing and Bus Bridging
Legacy peripheral interfacing often requires protocol translation between ISA, PCI, VME, or proprietary buses - an ideal role for the EPM7160SLC84-10N. With 64 user I/O pins, the device can implement a full 16-bit data bus plus control signals in a single chip, replacing multiple 74-series TTL glue chips. The 100 MHz fMAX internal counter rate supports high-speed state machines for DMA controllers and bus arbiters. Commercial temperature grade and 5V core operation match industrial backplane voltages, while JTAG ISP enables post-assembly bug fixes. Designers typically pair this CPLD with a microcontroller or microprocessor to handle high-level protocol logic.
Recommended
State Machine Control Logic
The EPM7160SLC84-10N excels at implementing complex finite state machines for sequencing, protocol handling, and control applications. Each of the 160 macrocells contains a programmable flip-flop with individual clock, clear, and preset controls, allowing parallel implementation of multiple state machines with different clock domains. The 4 Logic Array Blocks provide wide AND-OR product-term fan-in for state decoding, while the PIA (Programmable Interconnect Array) routes signals with predictable timing. With 175.4 MHz counter speed, the device can handle high-speed serial protocols, encoder/decoder logic, and PWM generation for motor or lighting control.
Recommended
Legacy System Maintenance and Re-Design
Many long-life-cycle products in industrial, military, and aerospace markets still use EPM7160SLC84-10N designs because the part is form-fit-function compatible with the original 84-pin PLCC footprint and JTAG programming chain. Maintenance engineers use this CPLD to add features to legacy boards without redesigning the PCB - simply reprogram the EEPROM via JTAG to update the logic. The -N (lead-free) variant supports modern RoHS-compliant assembly lines, while the original non-N variant preserves backward compatibility for non-RoHS manufacturing. This re-design use case is common in avionics, medical instrumentation, and process control systems with 15-20 year lifecycle requirements.
Recommended
Test Equipment and Instrumentation
Test and measurement instruments use the EPM7160SLC84-10N for pattern generation, timing control, and signal routing in ATE (Automatic Test Equipment) and bench instruments. The device's 10 ns tPD supports sub-100 MHz timing generation with predictable skew, while 64 I/O pins can drive multiple test points or relays. The EEPROM configuration ensures the test program loads deterministically at power-up, critical for production-floor repeatability. JTAG ISP allows engineers to load new test patterns in seconds without opening the instrument chassis, and the commercial temperature grade covers most laboratory environments. The 5V core and multi-voltage I/O match the TTL/CMOS logic families used in legacy instrumentation.
Recommended
Recommended Products Summary
Engineering reference data for EPM7160SLC84-10N β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM7160SLC84-10 | EPM7160ELC84-20 | EPM7160ELC84-15 | EPM7160ELC84-12 | EPM7160SLC84-6 |
|---|---|---|---|---|---|---|
| Package | 84-pin PLCC | 84-pin PLCC (same) | 84-pin PLCC (same) | 84-pin PLCC (same) | 84-pin PLCC (same) | 84-pin PLCC (same) |
| Brand | Intel | Intel | Intel | Intel | Intel | Intel |
| Family | MAX 7000S | MAX 7000S (same) | MAX 7000E | MAX 7000E | MAX 7000E | MAX 7000S (same) |
| Macrocells | 160 | 160 | 160 | 160 | 160 | 160 |
| Pin-to-Pin Delay (tPD) | 10 ns | 10 ns (same) | 20 ns (slower) | 15 ns (slower) | 12 ns (slightly slower) | 6 ns (faster) |
| Usable Gates | 3,200 | 3,200 | 3,200 | 3,200 | 3,200 | 3,200 |
| Lead-Free / RoHS | Yes (-N suffix) | No (non-N) | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] |
| Core Voltage (VCC) | 5.0 V | 5.0 V | 5.0 V | 5.0 V | 5.0 V | 5.0 V |
| JTAG ISP | Yes | Yes | Yes | Yes | Yes | Yes |
Key Differentiators
- Lead-free RoHS-compliant variant of legacy MAX 7000S design (vs EPM7160SLC84-10)
- Industry-standard 84-pin PLCC package with proven manufacturability (vs EPM7160EQC160-12)
- 10 ns tPD - faster than MAX 7000E alternatives (vs EPM7160ELC84-20)
Design Notes
The EPM7160SLC84-10N requires two supply rails: VCC at 5.0 V for the core logic and VCCIO at 3.3 V or 5.0 V for the I/O banks. Decouple each VCC pin with a 0.1 uF ceramic capacitor placed within 5 mm of the package pin, and add a 10 uF bulk capacitor per supply rail. Per the datasheet, when VCCIO is below 3.0 V the output timing delay increases slightly (tOD2 instead of tOD1) - keep VCCIO at 3.3 V nominal for standard timing. Power sequencing is not critical for this EEPROM-based device.
Place the JTAG header (TDI, TMS, TCK, TDO) on a 0.1-inch header or test points accessible without removing the board. The 84-pin PLCC socket should be a low-profile machined-pin type (e.g. 3M 84-pin PLCC socket) to allow easy device replacement. Keep high-speed signals (clock, JTAG) away from analog sections to minimize crosstalk. Route ground as a continuous plane under the device for thermal dissipation; the PLCC package dissipates up to 1.5 W at maximum toggle rate.
Do not confuse the EPM7160SLC84-10N with the EPM7160EQC160-12 (different package - 160-pin PQFP, not pin-compatible). Do not use VCCIO below 3.0 V or timing will degrade. The dedicated pins (GCLK1, GCLK3, OE1, OE2, GCLRn) cannot be repurposed as general I/O. Ensure all unused I/O pins are configured as outputs driving logic-low or tri-stated with pull-down to minimize power consumption and noise. The -N suffix is mandatory for RoHS-compliant assembly lines.
The 10 ns pin-to-pin delay sets the maximum combinational logic frequency; for register-to-register paths the fCNT of 175.4 MHz is the relevant limit. Use Quartus II (or MAX+PLUS II for legacy projects) timing analyzer to verify setup/hold margins on all flip-flop paths. Add 33 ohm series termination on clock outputs driving more than 2 inches of trace to reduce ringing. The PIA (Programmable Interconnect Array) introduces fixed routing delays - budget 2-4 ns for inter-LAB paths in your timing analysis.
Compliance Information
RoHS-compliant per -N suffix designation by Altera/Intel. Not AEC-Q100 qualified (commercial grade only, 0-70C). Halogen-free status not explicitly stated in available datasheets.
