EPM7160SLC84-15 vs EPM7160SLC84-10N Comparison

Detailed side-by-side comparison of EPM7160SLC84-15 by Altera and EPM7160SLC84-10N by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM7160SLC84-15 EPM7160SLC84-10N
Brand Altera Intel
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $10.80 $9.85
Family MAX 7000 MAX 7000S
Macrocells 160 β€”
Usable Gates 3,200 3,200 gates
Maximum Propagation Delay 15 ns β€”
Maximum User I/O Pins 64 β€”
Supply Voltage (VCCINT/VCIO) 4.75 V to 5.25 V (5 V nominal) β€”
I/O Logic Level Configurable 3.3 V or 5 V β€”
Technology CMOS, EEPROM configuration β€”
Package Type PLCC-84 (PQCC84, JEDEC S-PQCC-J84) β€”
Terminal Pitch 1.270 mm β€”
Mounting Type Surface Mount (PLCC socket or direct solder) Surface Mount
Operating Temperature 0 C to 70 C β€”
Programming Interface JTAG (IEEE 1149.1) in-system programmable β€”
RoHS Status Not RoHS compliant (contains lead, SnPb finish typical) β€”
Lifecycle Obsolete / last-time-buy (per Altera/Intel PDN) β€”
Logic Elements / Macrocells β€” 160 macrocells
Logic Array Blocks (LABs) β€” 4
User I/O Pins β€” 64 (also reported as 60 or 36 depending on variant)
Pin-to-Pin Delay (tPD) β€” 10 ns
Counter Speed (fCNT) β€” up to 175.4 MHz
Maximum Operating Frequency β€” 100 MHz
Supply Voltage - Core (VCC) β€” 5.0 V
I/O Supply Voltage (VCCIO) β€” 3.3 V or 5.0 V
Configuration Memory β€” EEPROM (non-volatile)
In-System Programming β€” Yes, via IEEE Std. 1149.1 JTAG
Program / Erase Cycles β€” 100 minimum
Data Retention β€” 20 years minimum
Package β€” 84-pin PLCC (J-lead, surface mount)
Operating Temperature Grade β€” Commercial (0C to +70C)
Lead-Free / RoHS β€” Yes (-N suffix indicates lead-free)

Datasheets & Resources

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