EPM7160SQC160-7 vs EPM7160SQC160-10 Comparison
Detailed side-by-side comparison of EPM7160SQC160-7 by Altera and EPM7160SQC160-10 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM7160SQC160-10 - MAX 7000S CPLD, 160 Macro Cells, 100MHz, PQFP-160 | Intel / Altera
EPM7160SQC160-10 ObsoleteSpecification Comparison
| Parameter | EPM7160SQC160-7 | EPM7160SQC160-10 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $9.75 | $12.20 |
| Family | MAX 7000S | MAX 7000S |
| Macrocells | 160 | β |
| Logic Array Blocks (LABs) | 10 | 10 |
| Usable System Gates | 3,200 | β |
| Product Terms per Macrocell | 32 | β |
| Maximum User I/Os | 104 | β |
| Global Clocks | 2 | β |
| Speed Grade | -7 (7.5 ns pin-to-pin) | β |
| Maximum Propagation Delay (tPD) | 7.5 ns | β |
| Supply Voltage (VCCINT) | 4.75 V to 5.25 V (5.0 V nominal) | 5.0 V |
| Program Memory Type | EEPROM (in-system programmable) | β |
| Operating Temperature | 0 Β°C to 70 Β°C (commercial) | 0 C to +70 C (commercial) |
| Package | 160-pin PQFP (BQFP, 28x28 mm) | PQFP-160 (SQC160) |
| Mounting Type | Surface Mount | Surface Mount |
| JTAG (IEEE 1149.1) | Yes (ISP via JTAG) | β |
| PCI Compliance | PCI Local Bus Specification Revision 2.2 | β |
| RoHS Status | Not Compliant (per Arrow listing) | unknown |
| Part Status | Obsolete | β |
| Macro Cells | β | 160 |
| Logic Elements / Gates | β | 3,200 usable gates |
| User I/Os | β | 104 |
| Maximum Operating Frequency | β | 100 MHz |
| Pin-to-Pin Propagation Delay (tPD) | β | 10 ns |
| I/O Voltage Tolerance | β | 5.0 V |
| Programming Technology | β | EEPROM, in-system programmable |
| JTAG Support | β | IEEE 1149.1 (boundary-scan + ISP) |
| Logic Family | β | CMOS |
| Process Technology | β | CMOS, EEPROM-based |
| Lead-Free | β | unknown |