EPM7160SQC160-7 vs EPM7160SQC160-10 比較
詳細並排比較 EPM7160SQC160-7 由 Altera 與 EPM7160SQC160-10 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
Altera
EPM7160SQC160-10 - MAX 7000S CPLD, 160 Macro Cells, 100MHz, PQFP-160 | Intel / Altera
EPM7160SQC160-10 Obsolete規格比較
| 參數 | EPM7160SQC160-7 | EPM7160SQC160-10 |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Family | MAX 7000S | MAX 7000S |
| Macrocells | 160 | — |
| Logic Array Blocks (LABs) | 10 | 10 |
| Usable System Gates | 3,200 | — |
| Product Terms per Macrocell | 32 | — |
| Maximum User I/Os | 104 | — |
| Global Clocks | 2 | — |
| Speed Grade | -7 (7.5 ns pin-to-pin) | — |
| Maximum Propagation Delay (tPD) | 7.5 ns | — |
| Supply Voltage (VCCINT) | 4.75 V to 5.25 V (5.0 V nominal) | 5.0 V |
| Program Memory Type | EEPROM (in-system programmable) | — |
| 工作溫度 | 0 °C to 70 °C (commercial) | 0 C to +70 C (commercial) |
| 封裝 | 160-pin PQFP (BQFP, 28x28 mm) | PQFP-160 (SQC160) |
| 安裝類型 | Surface Mount | Surface Mount |
| JTAG (IEEE 1149.1) | Yes (ISP via JTAG) | — |
| PCI Compliance | PCI Local Bus Specification Revision 2.2 | — |
| RoHS 狀態 | Not Compliant (per Arrow listing) | unknown |
| Part Status | Obsolete | — |
| Macro Cells | — | 160 |
| Logic Elements / Gates | — | 3,200 usable gates |
| User I/Os | — | 104 |
| Maximum Operating Frequency | — | 100 MHz |
| Pin-to-Pin Propagation Delay (tPD) | — | 10 ns |
| I/O Voltage Tolerance | — | 5.0 V |
| Programming Technology | — | EEPROM, in-system programmable |
| JTAG Support | — | IEEE 1149.1 (boundary-scan + ISP) |
| Logic Family | — | CMOS |
| Process Technology | — | CMOS, EEPROM-based |
| Lead-Free | — | unknown |