EPM7160SQC160-7 - 160-Macrocell MAX 7000S CPLD, 7.5ns | Altera
MPN: EPM7160SQC160-7 β End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $18.5 | $18.50 |
| 10 | $16.2 | $162.00 |
| 100 | $13.85 | $1,385.00 |
| 500 | $11.4 | $5,700.00 |
| 1,000 | $9.75 | $9,750.00 |
Drop-in alternatives for EPM7160SQC160-7 β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
EPM7160SQC160-6
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View Datasheet βEPM7160SQC160-10
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View Datasheet βEPM7160SQC160-10N
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View Datasheet βEPM7160EQC160-12
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View Datasheet βEPM7160SQC160-7
β Drop-Inβ In Stock
$9.75 / Unit
View Datasheet βEPM7160SQC160-7 Maximum Ratings & Electrical Characteristics
| Family | MAX 7000S |
| Macrocells | 160 |
| Logic Array Blocks (LABs) | 10 |
| Usable System Gates | 3,200 |
| Product Terms per Macrocell | 32 |
| Maximum User I/Os | 104 |
| Global Clocks | 2 |
| Speed Grade | -7 (7.5 ns pin-to-pin) |
| Maximum Propagation Delay (tPD) | 7.5 ns |
| Supply Voltage (VCCINT) | 4.75 V to 5.25 V (5.0 V nominal) |
| Program Memory Type | EEPROM (in-system programmable) |
| Operating Temperature | 0 Β°C to 70 Β°C (commercial) |
| Package | 160-pin PQFP (BQFP, 28x28 mm) |
| Mounting Type | Surface Mount |
| JTAG (IEEE 1149.1) | Yes (ISP via JTAG) |
| PCI Compliance | PCI Local Bus Specification Revision 2.2 |
| RoHS Status | Not Compliant (per Arrow listing) |
| Part Status | Obsolete |
EPM7160SQC160-7 Pin Configuration
| Pin 1 | I/O β General-purpose user I/O (bank 1) |
| Pin 2 | I/O β General-purpose user I/O (bank 1) |
| Pin 3 | I/O β General-purpose user I/O (bank 1) |
| Pin 4 | I/O β General-purpose user I/O (bank 1) |
| Pin 5 | I/O β General-purpose user I/O (bank 1) |
| Pin 6 | I/O β General-purpose user I/O (bank 1) |
| Pin 7 | I/O β General-purpose user I/O (bank 1) |
| Pin 8 | I/O β General-purpose user I/O (bank 1) |
| Pin 9 | I/O β General-purpose user I/O (bank 1) |
| Pin 10 | I/O β General-purpose user I/O (bank 1) |
| Pin 11 | GND β Ground |
| Pin 12 | I/O β General-purpose user I/O (bank 1) |
| Pin 13 | I/O β General-purpose user I/O (bank 1) |
| Pin 14 | I/O β General-purpose user I/O (bank 1) |
| Pin 15 | I/O β General-purpose user I/O (bank 1) |
| Pin 16 | I/O β General-purpose user I/O (bank 1) |
| Pin 17 | I/O β General-purpose user I/O (bank 1) |
| Pin 18 | I/O β General-purpose user I/O (bank 1) |
| Pin 19 | I/O β General-purpose user I/O (bank 1) |
| Pin 20 | I/O β General-purpose user I/O (bank 1) |
| Pin 21 | I/O β General-purpose user I/O (bank 2) |
| Pin 22 | I/O β General-purpose user I/O (bank 2) |
| Pin 23 | I/O β General-purpose user I/O (bank 2) |
| Pin 24 | I/O β General-purpose user I/O (bank 2) |
| Pin 25 | I/O β General-purpose user I/O (bank 2) |
| Pin 26 | I/O β General-purpose user I/O (bank 2) |
| Pin 27 | I/O β General-purpose user I/O (bank 2) |
| Pin 28 | I/O β General-purpose user I/O (bank 2) |
| Pin 29 | I/O β General-purpose user I/O (bank 2) |
| Pin 30 | GND β Ground |
| Pin 31 | I/O β General-purpose user I/O (bank 2) |
| Pin 32 | I/O β General-purpose user I/O (bank 2) |
| Pin 33 | I/O β General-purpose user I/O (bank 2) |
| Pin 34 | I/O β General-purpose user I/O (bank 2) |
| Pin 35 | I/O β General-purpose user I/O (bank 2) |
| Pin 36 | I/O β General-purpose user I/O (bank 2) |
| Pin 37 | I/O β General-purpose user I/O (bank 2) |
| Pin 38 | I/O β General-purpose user I/O (bank 2) |
| Pin 39 | I/O β General-purpose user I/O (bank 2) |
| Pin 40 | I/O β General-purpose user I/O (bank 2) |
| Pin 41 | GND β Ground |
| Pin 42 | I/O β General-purpose user I/O (bank 3) |
| Pin 43 | I/O β General-purpose user I/O (bank 3) |
| Pin 44 | I/O β General-purpose user I/O (bank 3) |
| Pin 45 | I/O β General-purpose user I/O (bank 3) |
| Pin 46 | I/O β General-purpose user I/O (bank 3) |
| Pin 47 | I/O β General-purpose user I/O (bank 3) |
| Pin 48 | I/O β General-purpose user I/O (bank 3) |
| Pin 49 | I/O β General-purpose user I/O (bank 3) |
| Pin 50 | I/O β General-purpose user I/O (bank 3) |
| Pin 51 | I/O β General-purpose user I/O (bank 3) |
| Pin 52 | GND β Ground |
| Pin 53 | I/O β General-purpose user I/O (bank 3) |
| Pin 54 | I/O β General-purpose user I/O (bank 3) |
| Pin 55 | I/O β General-purpose user I/O (bank 3) |
| Pin 56 | I/O β General-purpose user I/O (bank 3) |
| Pin 57 | I/O β General-purpose user I/O (bank 3) |
| Pin 58 | I/O β General-purpose user I/O (bank 3) |
| Pin 59 | I/O β General-purpose user I/O (bank 3) |
| Pin 60 | I/O β General-purpose user I/O (bank 3) |
| Pin 61 | I/O β General-purpose user I/O (bank 4) |
| Pin 62 | I/O β General-purpose user I/O (bank 4) |
| Pin 63 | GND β Ground |
| Pin 64 | I/O β General-purpose user I/O (bank 4) |
| Pin 65 | I/O β General-purpose user I/O (bank 4) |
| Pin 66 | I/O β General-purpose user I/O (bank 4) |
| Pin 67 | I/O β General-purpose user I/O (bank 4) |
| Pin 68 | I/O β General-purpose user I/O (bank 4) |
| Pin 69 | I/O β General-purpose user I/O (bank 4) |
| Pin 70 | I/O β General-purpose user I/O (bank 4) |
| Pin 71 | I/O β General-purpose user I/O (bank 4) |
| Pin 72 | I/O β General-purpose user I/O (bank 4) |
| Pin 73 | I/O β General-purpose user I/O (bank 4) |
| Pin 74 | GND β Ground |
| Pin 75 | I/O β General-purpose user I/O (bank 4) |
| Pin 76 | I/O β General-purpose user I/O (bank 4) |
| Pin 77 | I/O β General-purpose user I/O (bank 4) |
| Pin 78 | I/O β General-purpose user I/O (bank 4) |
| Pin 79 | I/O β General-purpose user I/O (bank 4) |
| Pin 80 | I/O β General-purpose user I/O (bank 4) |
| Pin 81 | I/O β General-purpose user I/O (bank 4) |
| Pin 82 | I/O β General-purpose user I/O (bank 4) |
| Pin 83 | I/O β General-purpose user I/O (bank 4) |
| Pin 84 | I/O β General-purpose user I/O (bank 4) |
| Pin 85 | GND β Ground |
| Pin 86 | I/O β General-purpose user I/O (bank 5) |
| Pin 87 | I/O β General-purpose user I/O (bank 5) |
| Pin 88 | I/O β General-purpose user I/O (bank 5) |
| Pin 89 | I/O β General-purpose user I/O (bank 5) |
| Pin 90 | I/O β General-purpose user I/O (bank 5) |
| Pin 91 | I/O β General-purpose user I/O (bank 5) |
| Pin 92 | I/O β General-purpose user I/O (bank 5) |
| Pin 93 | I/O β General-purpose user I/O (bank 5) |
| Pin 94 | I/O β General-purpose user I/O (bank 5) |
| Pin 95 | I/O β General-purpose user I/O (bank 5) |
| Pin 96 | GND β Ground |
| Pin 97 | I/O β General-purpose user I/O (bank 5) |
| Pin 98 | I/O β General-purpose user I/O (bank 5) |
| Pin 99 | I/O β General-purpose user I/O (bank 5) |
| Pin 100 | I/O β General-purpose user I/O (bank 5) |
| Pin 101 | I/O β General-purpose user I/O (bank 5) |
| Pin 102 | I/O β General-purpose user I/O (bank 5) |
| Pin 103 | I/O β General-purpose user I/O (bank 5) |
| Pin 104 | I/O β General-purpose user I/O (bank 5) |
| Pin 105 | I/O β General-purpose user I/O (bank 5) |
| Pin 106 | I/O β General-purpose user I/O (bank 5) |
| Pin 107 | GND β Ground |
| Pin 108 | I/O β General-purpose user I/O (bank 6) |
| Pin 109 | I/O β General-purpose user I/O (bank 6) |
| Pin 110 | I/O β General-purpose user I/O (bank 6) |
| Pin 111 | I/O β General-purpose user I/O (bank 6) |
| Pin 112 | I/O β General-purpose user I/O (bank 6) |
| Pin 113 | I/O β General-purpose user I/O (bank 6) |
| Pin 114 | I/O β General-purpose user I/O (bank 6) |
| Pin 115 | I/O β General-purpose user I/O (bank 6) |
| Pin 116 | I/O β General-purpose user I/O (bank 6) |
| Pin 117 | I/O β General-purpose user I/O (bank 6) |
| Pin 118 | GND β Ground |
| Pin 119 | I/O β General-purpose user I/O (bank 6) |
| Pin 120 | I/O β General-purpose user I/O (bank 6) |
| Pin 121 | I/O β General-purpose user I/O (bank 6) |
| Pin 122 | I/O β General-purpose user I/O (bank 6) |
| Pin 123 | I/O β General-purpose user I/O (bank 6) |
| Pin 124 | I/O β General-purpose user I/O (bank 6) |
| Pin 125 | I/O β General-purpose user I/O (bank 6) |
| Pin 126 | I/O β General-purpose user I/O (bank 6) |
| Pin 127 | I/O β General-purpose user I/O (bank 6) |
| Pin 128 | I/O β General-purpose user I/O (bank 6) |
| Pin 129 | GND β Ground |
| Pin 130 | I/O β General-purpose user I/O (bank 1) |
| Pin 131 | I/O β General-purpose user I/O (bank 1) |
| Pin 132 | I/O β General-purpose user I/O (bank 1) |
| Pin 133 | I/O β General-purpose user I/O (bank 1) |
| Pin 134 | I/O β General-purpose user I/O (bank 1) |
| Pin 135 | I/O β General-purpose user I/O (bank 1) |
| Pin 136 | I/O β General-purpose user I/O (bank 1) |
| Pin 137 | I/O β General-purpose user I/O (bank 1) |
| Pin 138 | I/O β General-purpose user I/O (bank 1) |
| Pin 139 | I/O β General-purpose user I/O (bank 1) |
| Pin 140 | GND β Ground |
| Pin 141 | I/O β General-purpose user I/O (bank 1) |
| Pin 142 | I/O β General-purpose user I/O (bank 1) |
| Pin 143 | I/O β General-purpose user I/O (bank 1) |
| Pin 144 | I/O β General-purpose user I/O (bank 1) |
| Pin 145 | I/O β General-purpose user I/O (bank 1) |
| Pin 146 | I/O β General-purpose user I/O (bank 1) |
| Pin 147 | I/O β General-purpose user I/O (bank 1) |
| Pin 148 | I/O β General-purpose user I/O (bank 1) |
| Pin 149 | I/O β General-purpose user I/O (bank 1) |
| Pin 150 | I/O β General-purpose user I/O (bank 1) |
| Pin 151 | GND β Ground |
| Pin 152 | TDI β JTAG Test Data In |
| Pin 153 | TMS β JTAG Test Mode Select |
| Pin 154 | TCK β JTAG Test Clock |
| Pin 155 | TDO β JTAG Test Data Out |
| Pin 156 | GND β Ground |
| Pin 157 | VCC β 5.0 V supply (4.75 V to 5.25 V) |
| Pin 158 | VCC β 5.0 V supply (4.75 V to 5.25 V) |
| Pin 159 | GLOBALCLK1 β Global clock input 1 |
| Pin 160 | GLOBALCLK2 β Global clock input 2 / OE |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM7160SQC160-7 is suitable for 6 applications: PCI Bus Glue Logic, Microprocessor to Memory Address Decoding, Bus-Width Translation (5 V to 3.3 V), State-Machine Replacement for Discrete PALs, Peripheral Controller Glue Logic, Industrial Control and Instrumentation Logic.
PCI Bus Glue Logic
The EPM7160SQC160-7's PCI-SIG 2.2 compliance and 104 user I/Os make it a natural fit for PCI target/host adapter glue logic. The 7.5 ns tPD allows state-machine decoding of PCI address/command phases within the 33 MHz bus clock period. Place the device between the PCI bus transceivers and the local controller to handle parity generation, target response, and burst-handling state. Compared to discrete 22V10 PALs, the 160-macrocell capacity consolidates what would otherwise require 4-6 SPLDs onto one BQFP-160 footprint.
Recommended
Microprocessor to Memory Address Decoding
In 8/16/32-bit embedded systems the EPM7160SQC160-7 replaces multiple 22V10 / GAL22V10 devices with a single 160-macrocell CPLD, generating chip-select signals for ROM, SRAM, DRAM, and peripheral banks. The 5.0 V VCC with selectable 3.3 V or 5.0 V output levels allows direct interfacing to both legacy 5 V memory and modern 3.3 V peripherals without external level shifters. The 7.5 ns tPD keeps the decoded chip-select valid before the memory access window opens at typical 25-40 MHz CPU clock rates.
Recommended
Bus-Width Translation (5 V to 3.3 V)
The EPM7160SQC160-7's selectable 3.3 V or 5.0 V output drivers per I/O bank enable mixed-voltage bus translation without external level-shift ICs. A 160-macrocell device comfortably implements a 32-bit bidirectional 5 V <-> 3.3 V translator with direction-control logic. The 7.5 ns tPD supports bus throughput up to ~66 MHz, suitable for legacy peripheral buses in industrial PCs and instrumentation where 5 V cores still coexist with 3.3 V ASICs.
Recommended
State-Machine Replacement for Discrete PALs
Engineers use the EPM7160SQC160-7 to consolidate boards originally built with 4-8 discrete PAL/GAL devices into a single CPLD, freeing PCB area and reducing BOM cost. The EEPROM-backed configuration is non-volatile, providing instant-on behavior at power-up - critical for industrial controllers where a slow FPGA boot is unacceptable. With 32 product terms per macrocell and 10 LABs, the device can host multiple independent state machines plus combinational decode in one chip, all running at the guaranteed 7.5 ns tPD.
Recommended
Peripheral Controller Glue Logic
The EPM7160SQC160-7 serves as the central glue-logic hub on legacy peripheral controller boards, interfacing microprocessors to UARTs, FIFOs, DMA controllers, and interrupt controllers. The 104 user I/Os and 3,200-gate capacity provide ample headroom for FIFO flag combining, interrupt prioritization, and timing generation. JTAG-based in-system programmability allows field firmware updates without removing the controller card from its host chassis - a key advantage over one-time-programmable PALs.
Recommended
Industrial Control and Instrumentation Logic
In industrial automation backplanes and test-and-measurement instruments, the EPM7160SQC160-7 delivers deterministic, non-volatile logic for custom timing, signal routing, and protection interlocks. The commercial 0-70 Β°C operating range covers most indoor enclosures, and the 5 V tolerance interfaces directly to legacy industrial sensors and actuators. The device's instant-on EEPROM configuration eliminates boot-loader complexity, making it ideal for safety-critical interlocks that must be active before the main CPU boots.
Recommended
Recommended Products Summary
Engineering reference data for EPM7160SQC160-7 β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM7160SQC160-6 | EPM7160SQC160-10 | EPM7160SQC160-10N | EPM7160EQC160-12 |
|---|---|---|---|---|---|
| Package | 160-pin PQFP (BQFP, 28x28 mm) | 160-pin PQFP (BQFP) - same | 160-pin PQFP (BQFP) - same | 160-pin PQFP (BQFP) - same | 160-pin PQFP (BQFP) - same |
| Brand | Altera | Altera | Altera | Altera | Altera |
| Speed Grade | -7 (7.5 ns tPD) | -6 (6 ns tPD) | -10 (10 ns tPD) | -10 (10 ns tPD) | -12 (12 ns tPD, MAX 7000E) |
| Macrocells | 160 | 160 | 160 | 160 | 160 |
| System Gates | 3,200 | 3,200 | 3,200 | 3,200 | 3,200 |
| Family | MAX 7000S | MAX 7000S | MAX 7000S | MAX 7000S | MAX 7000E |
| RoHS Status | Not Compliant | Not Compliant | Not Compliant | Lead-free / RoHS | Not Compliant |
| Operating Temperature | 0 to 70 Β°C (commercial) | 0 to 70 Β°C | 0 to 70 Β°C | 0 to 70 Β°C | 0 to 70 Β°C |
Key Differentiators
- Balanced speed-cost point in the MAX 7000S speed-grade family (vs EPM7160SQC160-6)
- PCI-SIG 2.2 compliant glue logic in a single chip (vs Discrete 22V10 / GAL22V10 PAL array)
- 5 V tolerant with selectable 3.3 V I/O for mixed-voltage designs (vs MAX V CPLD (5M160ZE64) active-lifecycle alternative)
Design Notes
The EPM7160SQC160-7 requires a single 5.0 V supply (4.75 V to 5.25 V). Decouple each VCC/GND pair with a 0.1 Β΅F X7R ceramic capacitor placed within 5 mm of the device leads, and add a single 10 Β΅F bulk tantalum or ceramic capacitor at the board's 5 V power entry. During in-system programming (ISP), transient current can briefly exceed the steady-state ICC; ensure the regulator has at least 200 mA headroom. Power sequencing is not required - the device enters user mode automatically after POR.
Route the four JTAG signals (TDI, TMS, TCK, TDO) as a short daisy-chain with 10 kΞ© pull-ups on TMS and TDI; keep total JTAG trace length below 50 mm to maintain signal integrity at typical 10-20 MHz TCK rates. The 160-pin PQFP (28x28 mm body) requires a 4-layer PCB with a solid ground plane beneath the device to provide a low-impedance return path for the 104 high-speed I/Os. Leave the four corner GND pins (11, 30, 41, 52, 63, 74, 85, 96, 107, 118, 129, 140, 151, 156) solidly stitched to the ground plane with multiple vias each for thermal and electrical performance.
Three pitfalls are common when migrating designs to or from the EPM7160SQC160-7. First, do not assume the I/O banks default to 5 V - the output level is set by VCCIO per bank and must be explicitly connected even when only one voltage is used. Second, do not exceed 104 user I/Os in your pin assignment; the datasheet's 'Maximum' count assumes all dedicated JTAG and global clock pins are re-purposed as I/O, which is rarely desirable. Third, when replacing with the EPM7160SQC160-6 or -10 speed grade, verify timing closure - the 25% speed delta (-10 vs -7) can break PCI-bus designs.
Compliance Information
Per Arrow listing: EU RoHS Not Compliant; ECCN EAR99; SVHC declaration Yes. Use EPM7160SQC160-10N suffix variant for lead-free / RoHS-compliant assembly. AEC-Q100 not applicable (commercial-grade part).
