EPM7256SRC208-15N vs EPM7256SQC208-15N Comparison
Detailed side-by-side comparison of EPM7256SRC208-15N by Altera and EPM7256SQC208-15N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM7256SRC208-15N
EPM7256SRC208-15N - MAX 7000S CPLD 256 Macro | Altera
EPM7256SRC208-15N ObsoleteAltera
EPM7256SQC208-15N
EPM7256SQC208-15N - MAX 7000S CPLD 256 Macrocell | Altera
EPM7256SQC208-15N ObsoleteSpecification Comparison
| Parameter | EPM7256SRC208-15N | EPM7256SQC208-15N |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $27.20 | $0.00 |
| Series | MAX 7000S | MAX 7000S |
| Macrocells | 256 | 256 |
| Usable Gates | 5,000 | β |
| User I/O Pins | 164 | 164 |
| Logic Array Blocks (LABs) | 16 | β |
| Pin-to-Pin Delay (tPD) | 15 ns | β |
| Maximum Counter Frequency | 76.9 MHz | β |
| Supply Voltage | 5 V | 5 V |
| Configuration Memory | EEPROM (non-volatile) | EEPROM (non-volatile) |
| Package | 208-pin RQFP (PowerQuad Flat Pack) | 208-pin PQFP |
| Mounting Type | Surface Mount | Surface Mount |
| Operating Temperature | 0C to +70C (commercial) | [DATA_NEEDED: operating temperature range] |
| In-System Programmability | Yes (IEEE 1149.1 JTAG) | Yes (ISP) |
| I/O Standard | 5 V TTL/CMOS compatible | β |
| RoHS Status | Compliant (N suffix) | Lead free / RoHS Compliant |
| Lead Free | Yes (N suffix) | β |
| MSL Level | [DATA_NEEDED: MSL level] | β |
| Number of Terminals | 208 | β |
| Pin-to-Pin Delay | β | 15 ns (speed grade -15) |
| JTAG Interface | β | IEEE 1149.1 boundary-scan |
| Logic Array Blocks | β | 16 macrocells per LAB |
| Interconnect | β | Programmable Interconnect Array (PIA) |
| Speed Grade | β | -15 |
| Product Category | β | CPLD - Complex Programmable Logic Devices |
| Manufacturer | β | Altera (Intel Programmable Solutions Group) |