EPM7256SRC208-15N vs EPM7256SQC208-15N Vergleich
Detaillierter Direktvergleich von EPM7256SRC208-15N von Altera und EPM7256SQC208-15N von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EPM7256SRC208-15N | EPM7256SQC208-15N |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $27,20 | $0,00 |
| Series | MAX 7000S | MAX 7000S |
| Macrocells | 256 | 256 |
| Usable Gates | 5,000 | — |
| User I/O Pins | 164 | 164 |
| Logic Array Blocks (LABs) | 16 | — |
| Pin-to-Pin Delay (tPD) | 15 ns | — |
| Maximum Counter Frequency | 76.9 MHz | — |
| Versorgungsspannung | 5 V | 5 V |
| Configuration Memory | EEPROM (non-volatile) | EEPROM (non-volatile) |
| Gehäuse | 208-pin RQFP (PowerQuad Flat Pack) | 208-pin PQFP |
| Montageart | Surface Mount | Surface Mount |
| Betriebstemperatur | 0C to +70C (commercial) | [DATA_NEEDED: operating temperature range] |
| In-System Programmability | Yes (IEEE 1149.1 JTAG) | Yes (ISP) |
| I/O Standard | 5 V TTL/CMOS compatible | — |
| RoHS-Status | Compliant (N suffix) | Lead free / RoHS Compliant |
| Lead Free | Yes (N suffix) | — |
| MSL-Level | [DATA_NEEDED: MSL level] | — |
| Number of Terminals | 208 | — |
| Pin-to-Pin Delay | — | 15 ns (speed grade -15) |
| JTAG Interface | — | IEEE 1149.1 boundary-scan |
| Logic Array Blocks | — | 16 macrocells per LAB |
| Interconnect | — | Programmable Interconnect Array (PIA) |
| Speed Grade | — | -15 |
| Product Category | — | CPLD - Complex Programmable Logic Devices |
| Manufacturer | — | Altera (Intel Programmable Solutions Group) |