EPM7256SRC208-15N vs EPM7256SQC208-15N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM7256SRC208-15N sa pamamagitan ng Altera at EPM7256SQC208-15N sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPM7256SRC208-15N | EPM7256SQC208-15N |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Series | MAX 7000S | MAX 7000S |
| Macrocells | 256 | 256 |
| Usable Gates | 5,000 | — |
| User I/O Pins | 164 | 164 |
| Logic Array Blocks (LABs) | 16 | — |
| Pin-to-Pin Delay (tPD) | 15 ns | — |
| Maximum Counter Frequency | 76.9 MHz | — |
| Volte ng Pagbibigay | 5 V | 5 V |
| Configuration Memory | EEPROM (non-volatile) | EEPROM (non-volatile) |
| Packhaging | 208-pin RQFP (PowerQuad Flat Pack) | 208-pin PQFP |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Temperature na Operasyon | 0C to +70C (commercial) | [DATA_NEEDED: operating temperature range] |
| In-System Programmability | Yes (IEEE 1149.1 JTAG) | Yes (ISP) |
| I/O Standard | 5 V TTL/CMOS compatible | — |
| Tindminan RoHS | Compliant (N suffix) | Lead free / RoHS Compliant |
| Lead Free | Yes (N suffix) | — |
| Level ng MSL | [DATA_NEEDED: MSL level] | — |
| Number of Terminals | 208 | — |
| Pin-to-Pin Delay | — | 15 ns (speed grade -15) |
| JTAG Interface | — | IEEE 1149.1 boundary-scan |
| Logic Array Blocks | — | 16 macrocells per LAB |
| Interconnect | — | Programmable Interconnect Array (PIA) |
| Speed Grade | — | -15 |
| Product Category | — | CPLD - Complex Programmable Logic Devices |
| Manufacturer | — | Altera (Intel Programmable Solutions Group) |