EPM9320ALC84-20 vs EPM9320LC84-20 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM9320ALC84-20 sa pamamagitan ng Altera at EPM9320LC84-20 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPM9320ALC84-20 | EPM9320LC84-20 |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | NRND | Obsolete |
| Family | MAX 9000 | MAX 9000 |
| Device Type | EPLD (Erasable Programmable Logic Device) | CPLD - Complex Programmable Logic Device |
| Macrocells | 320 | 320 |
| Logic Array Blocks (LABs) | 16 | — |
| Maximum User I/Os | 212 | — |
| Pin-to-Pin Delay (tPD) | 20 ns | — |
| Packhaging | PLCC-84 | PLCC-84 (Plastic Leaded Chip Carrier) |
| Process Technology | 0.5 µm CMOS EEPROM | — |
| Volte ng Pagbibigay | 5.0 V | 5.0 V |
| Programmability | In-system via IEEE 1149.1 JTAG | — |
| Temperature na Operasyon | [DATA_NEEDED: commercial or industrial grade] | 0 C to 70 C |
| Uri ng Pagpapasok | Surface Mount (PLCC socket compatible) | — |
| Configuration Memory | Non-volatile EEPROM | — |
| Boundary Scan | JTAG IEEE 1149.1 | — |
| Design Software | MAX+PLUS II / Quartus II (legacy) | — |
| Tindminan RoHS | [DATA_NEEDED: per Altera datasheet] | [DATA_NEEDED: RoHS status] |
| User I/Os | — | 60 |
| Logic Family | — | CMOS (EEPROM-based) |
| Pins | — | 84 |
| Propagation Delay (tPD) | — | 16 ns |
| Internal Counter Frequency | — | 118 MHz |
| In-System Programmability | — | Yes (IEEE 1149.1 JTAG) |
| Dedicated Inputs | — | 4 (global clock / clear / OE) |
| Architecture | — | Multiple Array MatriX (MAX), 3rd generation |
| PCI Compliance | — | PCI Local Bus Specification Rev. 2.2 |