EPM9320LC84-20 - MAX 9000 CPLD, 320 Macros, 84-PLCC | Altera
MPN: EPM9320LC84-20 ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $18.5 | $18.50 |
| 10 | $16.2 | $162.00 |
| 100 | $13.85 | $1,385.00 |
| 500 | $11.4 | $5,700.00 |
| 1,000 | $9.75 | $9,750.00 |
Drop-in alternatives for EPM9320LC84-20 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EPM9320LC84-15
✅ Drop-In✓ In Stock
$17.95 / Unit
View Datasheet →EPM9320LC84-10
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View Datasheet →EPM9320ALC84-20
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$10.5 / Unit
View Datasheet →EPM9320ALC84-15
✅ Drop-In✓ In Stock
$9.95 / Unit
View Datasheet →EPM9320ALI84-10
✅ Drop-In✓ In Stock
$19.95 / Unit
View Datasheet →EPM9320ALC84-10
✅ Drop-In✓ In Stock
$19.8 / Unit
View Datasheet →EPM9320LC84-20 Maximum Ratings & Electrical Characteristics
| Family | MAX 9000 |
| Device Type | CPLD - Complex Programmable Logic Device |
| Macrocells | 320 |
| User I/Os | 60 |
| Logic Family | CMOS (EEPROM-based) |
| Package | PLCC-84 (Plastic Leaded Chip Carrier) |
| Pins | 84 |
| Propagation Delay (tPD) | 16 ns |
| Internal Counter Frequency | 118 MHz |
| Supply Voltage | 5.0 V |
| Operating Temperature | 0 C to 70 C |
| In-System Programmability | Yes (IEEE 1149.1 JTAG) |
| Dedicated Inputs | 4 (global clock / clear / OE) |
| Architecture | Multiple Array MatriX (MAX), 3rd generation |
| PCI Compliance | PCI Local Bus Specification Rev. 2.2 |
EPM9320LC84-20 Pin Configuration
| Pin 1 | I/O — User I/O (assigned by Quartus fitter) |
| Pin 2 | I/O — User I/O (assigned by Quartus fitter) |
| Pin 3 | I/O — User I/O (assigned by Quartus fitter) |
| Pin 4 | I/O — User I/O (assigned by Quartus fitter) |
| Pin 5 | I/O — User I/O (assigned by Quartus fitter) |
| Pin 6 | I/O — User I/O (assigned by Quartus fitter) |
| Pin 7 | I/O — User I/O (assigned by Quartus fitter) |
| Pin 8 | I/O — User I/O (assigned by Quartus fitter) |
| Pin 9 | I/O — User I/O (assigned by Quartus fitter) |
| Pin 10 | I/O — User I/O (assigned by Quartus fitter) |
| Pin 11 | GND — Ground |
| Pin 12 | I/O — User I/O (assigned by Quartus fitter) |
| Pin 13 | I/O — User I/O (assigned by Quartus fitter) |
| Pin 14 | I/O — User I/O (assigned by Quartus fitter) |
| Pin 15 | I/O — User I/O (assigned by Quartus fitter) |
| Pin 16 | I/O — User I/O (assigned by Quartus fitter) |
| Pin 17 | I/O — User I/O (assigned by Quartus fitter) |
| Pin 18 | I/O — User I/O (assigned by Quartus fitter) |
| Pin 19 | I/O — User I/O (assigned by Quartus fitter) |
| Pin 20 | I/O — User I/O (assigned by Quartus fitter) |
| Pin 21 | GND — Ground |
| Pin 22 | I/O — User I/O (assigned by Quartus fitter) |
| Pin 23 | I/O — User I/O (assigned by Quartus fitter) |
| Pin 24 | I/O — User I/O (assigned by Quartus fitter) |
| Pin 25 | I/O — User I/O (assigned by Quartus fitter) |
| Pin 26 | I/O — User I/O (assigned by Quartus fitter) |
| Pin 27 | I/O — User I/O (assigned by Quartus fitter) |
| Pin 28 | I/O — User I/O (assigned by Quartus fitter) |
| Pin 29 | I/O — User I/O (assigned by Quartus fitter) |
| Pin 30 | I/O — User I/O (assigned by Quartus fitter) |
| Pin 31 | GND — Ground |
| Pin 32 | I/O — User I/O (assigned by Quartus fitter) |
| Pin 33 | I/O — User I/O (assigned by Quartus fitter) |
| Pin 34 | I/O — User I/O (assigned by Quartus fitter) |
| Pin 35 | I/O — User I/O (assigned by Quartus fitter) |
| Pin 36 | I/O — User I/O (assigned by Quartus fitter) |
| Pin 37 | I/O — User I/O (assigned by Quartus fitter) |
| Pin 38 | I/O — User I/O (assigned by Quartus fitter) |
| Pin 39 | I/O — User I/O (assigned by Quartus fitter) |
| Pin 40 | I/O — User I/O (assigned by Quartus fitter) |
| Pin 41 | GND — Ground |
| Pin 42 | IN4 — Dedicated input (global clock / clear / OE) |
| Pin 43 | IN3 — Dedicated input (global clock / clear / OE) |
| Pin 44 | IN2 — Dedicated input (global clock / clear / OE) |
| Pin 45 | IN1 — Dedicated input (global clock / clear / OE) |
| Pin 46 | I/O — User I/O (assigned by Quartus fitter) |
| Pin 47 | I/O — User I/O (assigned by Quartus fitter) |
| Pin 48 | I/O — User I/O (assigned by Quartus fitter) |
| Pin 49 | I/O — User I/O (assigned by Quartus fitter) |
| Pin 50 | I/O — User I/O (assigned by Quartus fitter) |
| Pin 51 | GND — Ground |
| Pin 52 | I/O — User I/O (assigned by Quartus fitter) |
| Pin 53 | I/O — User I/O (assigned by Quartus fitter) |
| Pin 54 | I/O — User I/O (assigned by Quartus fitter) |
| Pin 55 | I/O — User I/O (assigned by Quartus fitter) |
| Pin 56 | I/O — User I/O (assigned by Quartus fitter) |
| Pin 57 | I/O — User I/O (assigned by Quartus fitter) |
| Pin 58 | I/O — User I/O (assigned by Quartus fitter) |
| Pin 59 | I/O — User I/O (assigned by Quartus fitter) |
| Pin 60 | I/O — User I/O (assigned by Quartus fitter) |
| Pin 61 | GND — Ground |
| Pin 62 | TDI — JTAG Test Data In |
| Pin 63 | TMS — JTAG Test Mode Select |
| Pin 64 | TCK — JTAG Test Clock |
| Pin 65 | VCC — 5.0 V supply |
| Pin 66 | I/O — User I/O (assigned by Quartus fitter) |
| Pin 67 | I/O — User I/O (assigned by Quartus fitter) |
| Pin 68 | I/O — User I/O (assigned by Quartus fitter) |
| Pin 69 | I/O — User I/O (assigned by Quartus fitter) |
| Pin 70 | I/O — User I/O (assigned by Quartus fitter) |
| Pin 71 | GND — Ground |
| Pin 72 | I/O — User I/O (assigned by Quartus fitter) |
| Pin 73 | I/O — User I/O (assigned by Quartus fitter) |
| Pin 74 | I/O — User I/O (assigned by Quartus fitter) |
| Pin 75 | I/O — User I/O (assigned by Quartus fitter) |
| Pin 76 | I/O — User I/O (assigned by Quartus fitter) |
| Pin 77 | I/O — User I/O (assigned by Quartus fitter) |
| Pin 78 | I/O — User I/O (assigned by Quartus fitter) |
| Pin 79 | I/O — User I/O (assigned by Quartus fitter) |
| Pin 80 | I/O — User I/O (assigned by Quartus fitter) |
| Pin 81 | GND — Ground |
| Pin 82 | I/O — User I/O (assigned by Quartus fitter) |
| Pin 83 | I/O — User I/O (assigned by Quartus fitter) |
| Pin 84 | TDO — JTAG Test Data Out |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM9320LC84-20 is suitable for 6 applications: PCI Bus Interface Controller, Industrial Control Glue Logic, Telecom Line-Card Control Plane, Legacy Microprocessor Address Decoding, Test and Measurement Instrumentation, Multi-PAL Replacement and Board Consolidation.
PCI Bus Interface Controller
The EPM9320LC84-20's PCI Local Bus Specification Revision 2.2 compliance and 16 ns tPD make it well suited for implementing 33 MHz PCI target controllers, address decoding, and command-signal glue logic in 5 V embedded systems. The 320 macrocells comfortably absorb a full PCI state machine plus 4 to 6 address/data steering functions without partitioning. Deterministic timing from the on-chip EEPROM-backed macrocells eliminates the FPGA configuration-delay penalty that complicates cold-boot PCI enumeration. Compared with discrete 22V10 PALs, the EPM9320LC84-20 replaces 4 to 6 packages, freeing board area and simplifying the BOM. Designers should reserve the four dedicated global inputs for PCI CLK and RST# to meet the 7 ns PCI clock-to-out requirement, and use the dual-output macrocells to register combinatorial and registered logic independently.
Recommended
Industrial Control Glue Logic
In PLC and industrial-control backplanes, the EPM9320LC84-20 replaces dozens of 74LS series TTL gates and discrete PAL/GAL devices with a single 5 V programmable part. Its 60 user I/Os and 320 macrocells handle address decoding, watchdog timing, optocoupler interfacing, and isolated I/O expansion. The 0 to 70 C commercial operating range suits enclosed indoor cabinets, while the EEPROM-based ISP via JTAG allows field firmware updates without removing the board. The deterministic 16 ns tPD plus 118 MHz counter frequency supports stepper-motor pulse trains and encoder quadrature decoding at typical industrial rates up to 1 MHz. Compared with an FPGA-based equivalent, the EPM9320LC84-20 boots in microseconds (no configuration flash needed) and avoids in-rush current spikes that complicate 24 V supply designs.
Recommended
Telecom Line-Card Control Plane
Telecom line cards and channel banks have historically relied on 5 V MAX 9000 CPLDs for control-plane functions such as HDLC framing, timeslot switching glue, and alarm/status register aggregation. The EPM9320LC84-20's four dedicated low-skew global inputs fan out cleanly to 8 kHz frame-sync clocks, while 320 macrocells can absorb a full E1/T1 framer glue layer plus local register decoding. Its 5 V I/O directly drives legacy bus-interface ICs without level shifters, reducing BOM cost. PCI-compliance is a bonus for CompactPCI line cards. For new designs, evaluate MAX V CPLDs, but for maintenance of installed telecom infrastructure the EPM9320LC84-20 remains a qualified, deterministic control-plane engine.
Recommended
Legacy Microprocessor Address Decoding
The EPM9320LC84-20 is a natural fit for 5 V 68k, x86, and PowerPC-based embedded designs that require wide address-decode windows, chip-select generation, and wait-state insertion. With 320 macrocells the part can decode the full 24- or 32-bit address space of legacy processors and provide 16 to 24 active-low chip-select outputs while reserving macros for bus-watchdog logic. Its 16 ns tPD combined with a 25 MHz system clock gives approximately 24 ns of margin for address-to-CS timing, comfortably exceeding typical 68k and VME bus requirements. The PLCC-84 socket also simplifies bring-up and rework on prototype boards. For 3.3 V processors, migrate to the MAX V 5M240ZE64 family with appropriate level shifters.
Recommended
Test and Measurement Instrumentation
Bench-top instruments such as protocol analyzers, logic-analyzer front-ends, and ATE pin-electronics boards use the EPM9320LC84-20 for pattern generation, hand-shake sequencing, and front-panel switch matrix decoding. The 16 ns tPD supports pattern rates up to 60 MHz in pipelined designs, while 60 user I/Os accommodate 8 to 16 channels of digital I/O plus control signals. EEPROM-based ISP allows factory recalibration and feature upgrades via JTAG, eliminating the need for a separate configuration PROM. Compared with a microcontroller, the CPLD's deterministic response time eliminates software jitter, which is critical for timing-sensitive measurements. The PLCC-84 package is friendly to hand-rework in low-volume production.
Recommended
Multi-PAL Replacement and Board Consolidation
The EPM9320LC84-20 is widely deployed as a consolidation device replacing 4 to 6 standard 22V10 or 26V12 PALs on legacy boards. With 320 macrocells and 60 user I/Os, the part has roughly 6x the density of a 22V10, allowing net board-area savings of 30 to 50 percent along with reduced power consumption compared to bipolar PALs. Designers port the Boolean equations directly into Quartus or MAX+PLUS II using the legacy PAL-conversion flow. The CMOS EEPROM technology also eliminates the high standby current of bipolar PALs, an important consideration for battery-backed or solar-powered remote systems. This application is the canonical reason the EPM9320LC84-20 remains in active service despite its obsolete lifecycle status.
Recommended
Recommended Products Summary
Engineering reference data for EPM9320LC84-20 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM9320LC84-15 | EPM9320LC84-10 | EPM9320ALC84-20 | EPM9320ALC84-15 | EPM9320ALI84-10 |
|---|---|---|---|---|---|---|
| Brand | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) |
| Package | PLCC-84 | PLCC-84 (same) | PLCC-84 (same) | PLCC-84 (same) | PLCC-84 (same) | PLCC-84 (same) |
| Macrocells | 320 | 320 | 320 | 320 | 320 | 320 |
| User I/Os | 60 | 60 | 60 | 60 | 60 | 60 |
| Pin-to-Pin Delay (tPD) | 16 ns | 15 ns | 10 ns | 16 ns | 15 ns | 10 ns |
| Internal Counter Frequency | 118 MHz | 125 MHz (typ.) | 144 MHz | 118 MHz | 125 MHz (typ.) | 144 MHz |
| Supply Voltage | 5.0 V | 5.0 V | 5.0 V | 5.0 V | 5.0 V | 5.0 V |
| Operating Temperature | 0 C to 70 C (commercial) | 0 C to 70 C | 0 C to 70 C | 0 C to 70 C | 0 C to 70 C | -40 C to 85 C (industrial) |
| Silicon Revision | Original | Original | Original | 'A' revision | 'A' revision | 'A' revision + industrial |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
Key Differentiators
- Only 84-PLCC MAX 9000 part with 16 ns tPD and commercial temp range in active legacy demand (vs EPM9320LC84-15)
- Largest 84-PLCC macrocell count within the MAX 9000 family at the -20 speed grade (vs EPM7160SLC84-10)
- PLCC-84 socket footprint allows easy field replacement and board rework (vs EPM9320GC280-20)
Design Notes
The EPM9320LC84-20 requires a tightly regulated 5.0 V +/- 5% supply with bulk decoupling of at least 22 uF and a 0.1 uF ceramic bypass within 25 mm of each VCC pin (pins 65 and any VCC balls). Estimated: with 60 CMOS I/Os at 5.0 V toggling at 25 MHz, ICC is approximately 150 to 250 mA depending on loading. Use a separate analog 5 V plane or pi filter if the CPLD shares a rail with switching regulators. Add 4.7 uF + 0.1 uF at each PLCC socket corner to suppress simultaneous switching noise that could corrupt JTAG programming.
Mount the 84-pin PLCC in a through-hole or surface-mount socket (e.g., 3M Textool or PLCC SMT sockets) to ease firmware updates and avoid repeated thermal cycling of the CPLD. Provide at least 0.5 mm clearance around the package for probe access during in-system programming. Route the four dedicated global inputs (IN1-IN4, pins 42-45) as short matched-length traces (delta less than 5 mm) to minimize clock skew. Keep JTAG signals (TDI/TDO/TMS/TCK) away from high-speed I/O edges and add 10 kohm pull-ups on TDI and TMS to ensure a clean JTAG state at power-up.
Do not assume EPM9320 parts are RoHS-compliant - the original PLCC package used Pb-containing die attach and leads; verify material declaration before using in a RoHS end product. Do not substitute 5 V CPLDs into 3.3 V systems: the input thresholds will not register logic-high reliably and the outputs will over-drive 3.3 V rails. Always reserve one user I/O as a 'done' or 'init_done' signal to indicate successful JTAG ISP completion, and connect TRST to GND through a 1 kohm resistor if not used. When migrating from MAX+PLUS II to Quartus, re-run timing analysis because the Quartus fitter may produce different tCO and tSU numbers than MAX+PLUS II reported.
For designs that toggle outputs faster than 33 MHz (PCI) or drive long PCB traces, add 22 to 33 ohm series-termination resistors at the CPLD output to dampen reflections. The EPM9320 output edge rate is approximately 2 to 3 ns, so transmission-line effects appear above 200 mm trace lengths. Estimated: a 50 mm microstrip on FR4 (1 oz copper, 0.2 mm dielectric) has approximately 5 ns propagation delay - well below 16 ns tPD but adding to tCO. Use the four dedicated global inputs for any clock above 50 MHz and avoid routing clocks through LAB local routing.
Compliance Information
RoHS / lead-free / REACH status not present in the verified web data; the EPM9320LC84-20 predates the EU RoHS Directive and was originally released in a Pb-containing PLCC package. Newer factory-finished units may be supplied Pb-free but this must be verified per lot from the distributor's material declaration. AEC-Q100 is not applicable for this commercial-temperature CPLD.
