EPM9320ALC84-15 - MAX 9000 CPLD, 320 Macrocells, 16ns, 84-PLCC | Altera
MPN: EPM9320ALC84-15 β End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $18.5 | $18.50 |
| 10 | $16.2 | $162.00 |
| 100 | $13.75 | $1,375.00 |
| 500 | $11.4 | $5,700.00 |
| 1,000 | $9.95 | $9,950.00 |
Drop-in alternatives for EPM9320ALC84-15 β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
EPM9320ALC84-10
β Drop-Inβ In Stock
$19.8 / Unit
View Datasheet βEPM9320ALC84-10N
β Drop-Inβ In Stock
$21.4 / Unit
View Datasheet βEPM9320LC84-15
β Drop-Inβ In Stock
$17.95 / Unit
View Datasheet βEPM9320LI84-15
β Drop-Inπ Reference alternative (not in catalog)
EPM9320RI208-15
β Drop-Inπ Reference alternative (not in catalog)
EPM9320ALC84-15 Maximum Ratings & Electrical Characteristics
| Family | MAX 9000 CPLD |
| Macrocells | 320 |
| Usable Gates | 6000 |
| Propagation Delay (tPD) | 16 ns |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5 V nominal) |
| User I/O | 56 |
| Logic Array Blocks (LABs) | 16 |
| Technology | CMOS, EEPROM-based configuration |
| Package | 84-pin PLCC (S-PQCC-J84, J-lead) |
| Mounting Type | Through-hole / socket |
| Programming Interface | JTAG (IEEE 1149.1) / ISP |
| Operating Temperature | -40C to +85C (industrial) |
| Moisture Sensitivity Level (MSL) | MSL-3 (168 hours per fpgalink.com) |
| RoHS3 Compliance | ROHS3 Compliant (per fpgalink.com listing) |
EPM9320ALC84-15 Pin Configuration
| Pin 1 | I/O β User I/O (bank 1) |
| Pin 2 | I/O β User I/O (bank 1) |
| Pin 3 | I/O β User I/O (bank 1) |
| Pin 4 | I/O β User I/O (bank 1) |
| Pin 5 | I/O β User I/O (bank 1) |
| Pin 6 | I/O β User I/O (bank 1) |
| Pin 7 | VCC β 5 V supply (core/I/O bank 1) |
| Pin 8 | I/O β User I/O (bank 1) |
| Pin 9 | I/O β User I/O (bank 1) |
| Pin 10 | I/O β User I/O (bank 1) |
| Pin 11 | I/O β User I/O (bank 1) |
| Pin 12 | TDI β JTAG Test Data In |
| Pin 13 | I/O β User I/O (bank 1) |
| Pin 14 | I/O β User I/O (bank 1) |
| Pin 15 | VCC β 5 V supply (bank 1) |
| Pin 16 | I/O β User I/O (bank 1) |
| Pin 17 | I/O β User I/O (bank 1) |
| Pin 18 | I/O β User I/O (bank 1) |
| Pin 19 | I/O β User I/O (bank 1) |
| Pin 20 | I/O β User I/O (bank 1) |
| Pin 21 | GND β Ground |
| Pin 22 | I/O β User I/O (bank 2) |
| Pin 23 | I/O β User I/O (bank 2) |
| Pin 24 | I/O β User I/O (bank 2) |
| Pin 25 | I/O β User I/O (bank 2) |
| Pin 26 | I/O β User I/O (bank 2) |
| Pin 27 | I/O β User I/O (bank 2) |
| Pin 28 | I/O β User I/O (bank 2) |
| Pin 29 | TMS β JTAG Test Mode Select |
| Pin 30 | TCK β JTAG Test Clock |
| Pin 31 | I/O β User I/O (bank 2) |
| Pin 32 | I/O β User I/O (bank 2) |
| Pin 33 | VCC β 5 V supply (bank 2) |
| Pin 34 | I/O β User I/O (bank 2) |
| Pin 35 | I/O β User I/O (bank 2) |
| Pin 36 | I/O β User I/O (bank 2) |
| Pin 37 | I/O β User I/O (bank 2) |
| Pin 38 | I/O β User I/O (bank 2) |
| Pin 39 | I/O β User I/O (bank 2) |
| Pin 40 | I/O β User I/O (bank 2) |
| Pin 41 | GND β Ground |
| Pin 42 | I/O β User I/O (bank 3) |
| Pin 43 | I/O β User I/O (bank 3) |
| Pin 44 | I/O β User I/O (bank 3) |
| Pin 45 | I/O β User I/O (bank 3) |
| Pin 46 | I/O β User I/O (bank 3) |
| Pin 47 | I/O β User I/O (bank 3) |
| Pin 48 | I/O β User I/O (bank 3) |
| Pin 49 | I/O β User I/O (bank 3) |
| Pin 50 | I/O β User I/O (bank 3) |
| Pin 51 | I/O β User I/O (bank 3) |
| Pin 52 | I/O β User I/O (bank 3) |
| Pin 53 | VCC β 5 V supply (bank 3) |
| Pin 54 | I/O β User I/O (bank 3) |
| Pin 55 | I/O β User I/O (bank 3) |
| Pin 56 | I/O β User I/O (bank 3) |
| Pin 57 | GND β Ground |
| Pin 58 | I/O β User I/O (bank 4) |
| Pin 59 | I/O β User I/O (bank 4) |
| Pin 60 | I/O β User I/O (bank 4) |
| Pin 61 | I/O β User I/O (bank 4) |
| Pin 62 | I/O β User I/O (bank 4) |
| Pin 63 | I/O β User I/O (bank 4) |
| Pin 64 | I/O β User I/O (bank 4) |
| Pin 65 | I/O β User I/O (bank 4) |
| Pin 66 | I/O β User I/O (bank 4) |
| Pin 67 | I/O β User I/O (bank 4) |
| Pin 68 | GND β Ground |
| Pin 69 | I/O β User I/O (bank 4) |
| Pin 70 | I/O β User I/O (bank 4) |
| Pin 71 | I/O β User I/O (bank 4) |
| Pin 72 | TDO β JTAG Test Data Out |
| Pin 73 | GCLK1 β Global clock 1 |
| Pin 74 | GCLK2 β Global clock 2 |
| Pin 75 | OE1/GCLK3 β Output enable 1 / Global clock 3 |
| Pin 76 | OE2/GCLK4 β Output enable 2 / Global clock 4 |
| Pin 77 | GCLR β Global clear |
| Pin 78 | I/O β User I/O (bank 4) |
| Pin 79 | I/O β User I/O (bank 4) |
| Pin 80 | I/O β User I/O (bank 4) |
| Pin 81 | VCC β 5 V supply (bank 4) |
| Pin 82 | I/O β User I/O (bank 4) |
| Pin 83 | I/O β User I/O (bank 4) |
| Pin 84 | I/O β User I/O (bank 4) |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM9320ALC84-15 is suitable for 6 applications: 5 V Industrial PLC Glue Logic, ISA/PCI Bus Address Decoding & Chip-Select Generation, Motor Control State Machines, Telecom Backplane Control Logic, Legacy ASIC Replacement, Embedded System Glue Logic.
5 V Industrial PLC Glue Logic
The EPM9320ALC84-15 is well-suited to 5 V industrial PLC glue-logic integration: its 320 macrocells and 56 I/O easily absorb address decoding, peripheral chip-select generation, and timer/counter fan-out for legacy PLC backplanes. With a 16 ns worst-case tPD, the part deterministically meets timing of 25 MHz state machines commonly used in PLC scan loops. The 84-pin PLCC socket-mount format supports field-replacement and long-lifecycle industrial maintenance, while JTAG ISP allows firmware updates without removing the board. Compared with stitching multiple 22V10 SPLDs, this CPLD reduces board area and improves noise margin by replacing discrete glue logic with a single 5 V device.
Recommended
ISA/PCI Bus Address Decoding & Chip-Select Generation
In ISA or PCI bus address decoding, the EPM9320ALC84-15's 56 I/O and 16 LABs provide enough macrocells to decode the full 24-bit address bus and generate 8 to 12 peripheral chip-selects in a single device. Its 16 ns tPD adds minimal latency to bus cycles, and the deterministic interconnect guarantees that any chip-select arrives within the same window regardless of which macrocell synthesizes it. Designers typically pair this part with 5 V-tolerant bus transceivers and use the JTAG port for ISP of updated decode maps. The PLCC-84 socket also makes this a common insertion point for legacy PC/104 and VMEbus controllers where the bus architecture predates modern PLD/FPGA tooling.
Recommended
Motor Control State Machines
For stepper and BLDC motor control, the EPM9320ALC84-15 synthesizes the commutation state machine, PWM blanking logic, and fault handlers in a single 5 V device. With 16 LABs and 320 macrocells, the design can encode full sinusoidal commutation tables and quadrature decoders without external logic; the 16 ns tPD keeps the loop tight enough for 50 kHz PWM rates. The PLCC-84 package is preferred in motor drives for its thermal headroom at high ambient temperatures. JTAG ISP enables field updates of control firmware, while the deterministic timing ensures uniform PWM edge placement across all channels - critical for low-noise motor operation.
Recommended
Telecom Backplane Control Logic
The EPM9320ALC84-15 integrates backplane control logic in T1/E1 and legacy SDH/SONET systems where 5 V tolerance and deterministic timing are required. Its 56 I/O can absorb clock-distribution trees, alarm-input scanning, and LED-status drivers that would otherwise require multiple PALs. The 16 ns tPD is comfortably fast for backplane housekeeping buses operating below 30 MHz, while the PLCC-84 package withstands the conformal coating and extended temperature of telecom cabinets. JTAG boundary-scan enables in-service board test, an important feature for the long service life of central-office equipment.
Recommended
Legacy ASIC Replacement
The EPM9320ALC84-15 is a classic ASIC replacement for end-of-life gate arrays in long-lifecycle medical, aerospace, and industrial-control products. With 320 macrocells and 6 K usable gates, it absorbs medium-complexity ASICs from the 1990s, and the JTAG ISP interface allows last-minute design changes without re-spinning masks. The 84-PLCC socket simplifies field service and qualification - legacy ASICs in non-standard packages are notoriously hard to second-source. Designers keep the 16 ns tPD margin for legacy timing budgets while benefiting from a programmable, software-defined implementation that reduces NRE.
Recommended
Embedded System Glue Logic
In embedded designs built around legacy x86, 68k, or PowerPC processors, the EPM9320ALC84-15 consolidates chip-select, wait-state, and interrupt-priority logic in a single 5 V device. The 56 user I/O handle eight to twelve peripheral selects plus interrupt controllers, and the 16 LABs accommodate address-decoding tables up to 16-bit wide. The deterministic 16 ns tPD ensures that processor-side accesses to slow peripherals remain within the bus-cycle budget. The PLCC-84 package is widely supported on embedded SBCs (PC/104, VME), and JTAG ISP allows remote firmware updates via boundary-scan tools in production.
Recommended
Recommended Products Summary
Engineering reference data for EPM9320ALC84-15 β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM9320ALC84-10 | EPM9320ALC84-10N | EPM9320LC84-15 | EPM9320LI84-15 |
|---|---|---|---|---|---|
| Brand | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) |
| Package | 84-pin PLCC (S-PQCC-J84) | 84-pin PLCC - same | 84-pin PLCC - same | 84-pin PLCC - same | 84-pin PLCC - same |
| Macrocells | 320 | 320 | 320 | 320 | 320 |
| Propagation Delay (tPD) | 16 ns | 10 ns | 10 ns | 16 ns | 16 ns |
| Temperature Grade | Industrial (-40C to +85C) | Industrial (-40C to +85C) | Industrial (-40C to +85C) | Commercial (0C to +70C) | Industrial (-40C to +85C) |
| Supply Voltage | 4.75 V to 5.25 V | 4.75 V to 5.25 V | 4.75 V to 5.25 V | 4.75 V to 5.25 V | 4.75 V to 5.25 V |
| Lead-Free Finish | [DATA_NEEDED] | [DATA_NEEDED] | Pb-free (N suffix) | [DATA_NEEDED] | Pb-free (N suffix implied) |
| User I/O | 56 | 56 | 56 | 56 | 56 |
Key Differentiators
- 320 macrocells in a single 84-PLCC package with deterministic 16 ns tPD (vs EPM9320ALC84-10)
- Industrial temperature grade (-40C to +85C) with EEPROM non-volatility (vs EPM9320LC84-15)
- In-system programmability via IEEE 1149.1 JTAG, no boot PROM required (vs EPM7160SLC84-10 (MAX 7000 family))
- 6 K usable gates with 16 LABs - higher density than 22V10/32V16 SPLDs (vs Multiple PALCE22V10 SPLDs)
Design Notes
The EPM9320ALC84-15 requires a single 4.75 V to 5.25 V supply with adequate decoupling. Place 0.1 uF ceramic bypass capacitors within 5 mm of each VCC pin (the 84-PLCC exposes VCC on pins 7, 15, 33, 53, 81). A bulk 10 uF tantalum or ceramic cap on the supply rail handles transient switching current during simultaneous I/O toggling. Estimated: at 56 I/O switching at 10 MHz, peak supply current can reach ~150 mA; budget for 300 mA worst case in the regulator. Connect all five GND pins (21, 41, 57, 68) directly to a low-impedance ground plane.
When laying out the 84-pin PLCC socket, fan out the inner ring of pins on the top layer with vias to an inner power/ground split plane. The MAX 9000's deterministic interconnect requires no special signal-integrity routing, but keep JTAG traces (TDI/TDO/TMS/TCK) short and isolated from switching outputs. Estimated: a 4-layer PCB with 1 oz copper and a 0.5 oz inner ground plane comfortably meets the 16 ns timing budget; for 10 ns drop-in operation use 2 oz copper on signal layers. Avoid 90-degree bends on clock pins GCLK1/GCLK2 to preserve duty cycle.
Do not confuse speed grade '15' (16 ns) with '10' (10 ns) or '12' (12 ns) - all three grades share the same 84-PLCC pinout and JTAG, but the tPD differs by up to 60%. For designs migrating from the MAX 7000 family, note that the MAX 9000 uses different programming files; re-compile in MAX+PLUS II or Quartus before loading the JTAG image. Estimated: typical I_OL/I_OH drive is 8 mA per pin in 5 V mode, sufficient for LED drive but inadequate for bus termination - place external buffers for backplane signals. Also note that the 'LC' suffix denotes commercial temperature, not 'lead-free'.
Compliance Information
ROHS3 Compliant per fpgalink.com listing (third-party distributor attestation). REACH and AEC-Q100 status not in verified data. Industrial temp grade (-40C to +85C) is appropriate for industrial but NOT automotive AEC-Q100 qualified.
