EPM9320AR1208-10 vs EPM9320ARI208-10N Comparison
Detailed side-by-side comparison of EPM9320AR1208-10 by Altera and EPM9320ARI208-10N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM9320AR1208-10 - MAX 9000 EPLD, 1208-Pin PGA, 10ns | Intel / Altera
EPM9320AR1208-10 ObsoleteAltera
EPM9320ARI208-10N - MAX 9000 CPLD, 320 Macrocells, 208-RQFP | Altera
EPM9320ARI208-10N ObsoleteSpecification Comparison
| Parameter | EPM9320AR1208-10 | EPM9320ARI208-10N |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $159.00 | $16.20 |
| Product Family | MAX 9000 | β |
| Device Type | EPLD (Erasable Programmable Logic Device) | β |
| Logic Density | 6,000 usable gates | β |
| Macrocells | [DATA_NEEDED: macrocell count] | 320 |
| Logic Array Blocks (LABs) | [DATA_NEEDED: LAB count] | 20 |
| Pin-to-Pin Delay (tPD) | 10 ns | β |
| Maximum Frequency (fMAX) | [DATA_NEEDED: fMAX in MHz] | β |
| Process Technology | 0.7 Β΅m CMOS EEPROM | CMOS EEPROM |
| Package Type | PGA-1208 (Pin Grid Array) | β |
| Package Code | AR1208 | β |
| Pin Count | 1208 | β |
| Mounting Type | Through-Hole (Pin Grid Array socket) | Surface Mount |
| Operating Temperature | [DATA_NEEDED: commercial/industrial/military grade] | -40 C to +85 C (industrial) |
| Supply Voltage | 5 V (typical) | 4.5 V to 5.5 V |
| Programming Interface | IEEE 1149.1 JTAG (ByteBlaster compatible) | β |
| RoHS Status | [DATA_NEEDED: RoHS compliance - legacy part] | unknown |
| Lead-Free | [DATA_NEEDED: lead-free status] | β |
| Family | β | MAX 9000 |
| Product Type | β | CPLD (Complex Programmable Logic Device) |
| Usable Gates | β | 6,000 |
| Maximum Operating Frequency | β | 144.9 MHz |
| Propagation Delay (tPD) | β | 10 ns (speed grade -10) |
| Package | β | 208-pin RQFP (S-PQFP-G208) |
| Programmability | β | In-system (ISP) via IEEE 1149.1 JTAG |
| Global Dedicated Inputs | β | 16 |
| Architecture | β | Multiple Array MatriX (MAX) third-generation |