EPM9320AR1208-10 vs EPM9320ARI208-10N 比較
詳細並排比較 EPM9320AR1208-10 由 Altera 與 EPM9320ARI208-10N 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
Altera
EPM9320AR1208-10 - MAX 9000 EPLD, 1208-Pin PGA, 10ns | Intel / Altera
EPM9320AR1208-10 ObsoleteAltera
EPM9320ARI208-10N - MAX 9000 CPLD, 320 Macrocells, 208-RQFP | Altera
EPM9320ARI208-10N Obsolete規格比較
| 參數 | EPM9320AR1208-10 | EPM9320ARI208-10N |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Product Family | MAX 9000 | — |
| Device Type | EPLD (Erasable Programmable Logic Device) | — |
| Logic Density | 6,000 usable gates | — |
| Macrocells | [DATA_NEEDED: macrocell count] | 320 |
| Logic Array Blocks (LABs) | [DATA_NEEDED: LAB count] | 20 |
| Pin-to-Pin Delay (tPD) | 10 ns | — |
| Maximum Frequency (fMAX) | [DATA_NEEDED: fMAX in MHz] | — |
| Process Technology | 0.7 µm CMOS EEPROM | CMOS EEPROM |
| Package Type | PGA-1208 (Pin Grid Array) | — |
| Package Code | AR1208 | — |
| 腳位數 | 1208 | — |
| 安裝類型 | Through-Hole (Pin Grid Array socket) | Surface Mount |
| 工作溫度 | [DATA_NEEDED: commercial/industrial/military grade] | -40 C to +85 C (industrial) |
| 供應電壓 | 5 V (typical) | 4.5 V to 5.5 V |
| Programming Interface | IEEE 1149.1 JTAG (ByteBlaster compatible) | — |
| RoHS 狀態 | [DATA_NEEDED: RoHS compliance - legacy part] | unknown |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Family | — | MAX 9000 |
| Product Type | — | CPLD (Complex Programmable Logic Device) |
| Usable Gates | — | 6,000 |
| Maximum Operating Frequency | — | 144.9 MHz |
| Propagation Delay (tPD) | — | 10 ns (speed grade -10) |
| 封裝 | — | 208-pin RQFP (S-PQFP-G208) |
| Programmability | — | In-system (ISP) via IEEE 1149.1 JTAG |
| Global Dedicated Inputs | — | 16 |
| Architecture | — | Multiple Array MatriX (MAX) third-generation |