EPM9320AR1208-10 vs EPM9320ARI208-10N 对比

详细并排对比 EPM9320AR1208-10 出自 Altera 和 EPM9320ARI208-10N 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPM9320AR1208-10 EPM9320ARI208-10N
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete Obsolete
库存状态 有库存 有库存
单价(USD) $159.00 $16.20
Product Family MAX 9000 —
Device Type EPLD (Erasable Programmable Logic Device) —
Logic Density 6,000 usable gates —
Macrocells [DATA_NEEDED: macrocell count] 320
Logic Array Blocks (LABs) [DATA_NEEDED: LAB count] 20
Pin-to-Pin Delay (tPD) 10 ns —
Maximum Frequency (fMAX) [DATA_NEEDED: fMAX in MHz] —
Process Technology 0.7 µm CMOS EEPROM CMOS EEPROM
Package Type PGA-1208 (Pin Grid Array) —
Package Code AR1208 —
引脚数量 1208 —
安装类型 Through-Hole (Pin Grid Array socket) Surface Mount
工作温度 [DATA_NEEDED: commercial/industrial/military grade] -40 C to +85 C (industrial)
电源电压 5 V (typical) 4.5 V to 5.5 V
Programming Interface IEEE 1149.1 JTAG (ByteBlaster compatible) —
RoHS 状态 [DATA_NEEDED: RoHS compliance - legacy part] unknown
Lead-Free [DATA_NEEDED: lead-free status] —
Family — MAX 9000
Product Type — CPLD (Complex Programmable Logic Device)
Usable Gates — 6,000
Maximum Operating Frequency — 144.9 MHz
Propagation Delay (tPD) — 10 ns (speed grade -10)
封装 — 208-pin RQFP (S-PQFP-G208)
Programmability — In-system (ISP) via IEEE 1149.1 JTAG
Global Dedicated Inputs — 16
Architecture — Multiple Array MatriX (MAX) third-generation

数据手册与资源

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