EPM9320AR1208-10 vs EPM9320ARI208-10N Comparaison
Comparaison détaillée côte à côte de EPM9320AR1208-10 par Altera et EPM9320ARI208-10N par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Altera
EPM9320AR1208-10 - MAX 9000 EPLD, 1208-Pin PGA, 10ns | Intel / Altera
EPM9320AR1208-10 ObsoleteAltera
EPM9320ARI208-10N - MAX 9000 CPLD, 320 Macrocells, 208-RQFP | Altera
EPM9320ARI208-10N ObsoleteComparaison des spécifications
| Paramètre | EPM9320AR1208-10 | EPM9320ARI208-10N |
|---|---|---|
| Marque | Altera | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $159,00 | $16,20 |
| Product Family | MAX 9000 | — |
| Device Type | EPLD (Erasable Programmable Logic Device) | — |
| Logic Density | 6,000 usable gates | — |
| Macrocells | [DATA_NEEDED: macrocell count] | 320 |
| Logic Array Blocks (LABs) | [DATA_NEEDED: LAB count] | 20 |
| Pin-to-Pin Delay (tPD) | 10 ns | — |
| Maximum Frequency (fMAX) | [DATA_NEEDED: fMAX in MHz] | — |
| Process Technology | 0.7 µm CMOS EEPROM | CMOS EEPROM |
| Package Type | PGA-1208 (Pin Grid Array) | — |
| Package Code | AR1208 | — |
| Nombre de broches | 1208 | — |
| Type de montage | Through-Hole (Pin Grid Array socket) | Surface Mount |
| Température de fonctionnement | [DATA_NEEDED: commercial/industrial/military grade] | -40 C to +85 C (industrial) |
| Tension d'alimentation | 5 V (typical) | 4.5 V to 5.5 V |
| Programming Interface | IEEE 1149.1 JTAG (ByteBlaster compatible) | — |
| Statut RoHS | [DATA_NEEDED: RoHS compliance - legacy part] | unknown |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Family | — | MAX 9000 |
| Product Type | — | CPLD (Complex Programmable Logic Device) |
| Usable Gates | — | 6,000 |
| Maximum Operating Frequency | — | 144.9 MHz |
| Propagation Delay (tPD) | — | 10 ns (speed grade -10) |
| Boîtier | — | 208-pin RQFP (S-PQFP-G208) |
| Programmability | — | In-system (ISP) via IEEE 1149.1 JTAG |
| Global Dedicated Inputs | — | 16 |
| Architecture | — | Multiple Array MatriX (MAX) third-generation |