EPM9320ARC208-10 vs EPM9320ARC208-10N Comparison
Detailed side-by-side comparison of EPM9320ARC208-10 by Altera and EPM9320ARC208-10N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM9320ARC208-10 | EPM9320ARC208-10N |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Last Time Buy | Obsolete |
| Device Family | MAX 9000 | — |
| Product Type | CPLD (Complex Programmable Logic Device) | — |
| Macrocells | 320 | — |
| Usable Gates | 6,000 | — |
| Pin-to-Pin Delay (tPD) | 10 ns | — |
| Maximum Frequency | 144.9 MHz | 144.9 MHz |
| Supply Voltage | 5.0 V | — |
| Logic Blocks (LABs) | 16 | — |
| Programmability | EEPROM, in-system programmable via JTAG | — |
| JTAG Support | IEEE Std. 1149.1 compliant | — |
| Speed/Power Optimization | Per-macrocell programmable, 50% power mode available | — |
| Package | RQFP-208 (Power Quad Flat Pack) | 208-pin RQFP (BFQFP with exposed pad) |
| Mounting Type | Surface Mount | Surface Mount |
| Operating Temperature | [DATA_NEEDED: operating temperature range] | 0C to +70C (Commercial) |
| RoHS Status | [DATA_NEEDED: RoHS compliance status] | Compliant (lead-free 'N' suffix) |
| Family | — | MAX 9000 |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Macro Cells | — | 320 |
| Logic Gates | — | 6,000 gates |
| Logic Array Blocks (LABs) | — | 16 |
| Propagation Delay (tPD) | — | 10 ns |
| Supply Voltage (VCC) | — | 5 V |
| User I/O Pins | — | 168 |
| Dedicated Input Pins | — | 12 |
| Programming Interface | — | IEEE Std. 1149.1 JTAG |
| Configuration Memory | — | Non-volatile EEPROM |