EPM9320LC84-10 vs EPM9320LC84-20N Comparison

Detailed side-by-side comparison of EPM9320LC84-10 by Intel and EPM9320LC84-20N by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM9320LC84-10 EPM9320LC84-20N
Brand Intel Intel
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status NRND Active
Family MAX 9000 EPLD —
Device EPM9320 —
Macrocells 320 320
Usable Gates 6000 (typical) 6,000
Logic Array Blocks (LABs) 16 —
Maximum User I/O Pins 168 (varies by package) —
Pin-to-Pin Logic Delay (tPD) 10 ns —
Maximum Frequency (fCNT) [DATA_NEEDED: fCNT in MHz] —
Supply Voltage (VCC) 5.0 V (typical, see datasheet) 5 V
Process Technology 0.7 µm CMOS EEPROM/UV-EPROM —
Package 84-pin PLCC (JEDEC MO-047) —
Mounting Type Surface Mount (PLCC socket also common) Surface Mount (J-bend)
Operating Temperature 0C to +70C (commercial) [DATA_NEEDED: exact grade suffix] 0 C to +70 C (Commercial)
Programming Interface JTAG (IEEE 1149.1) boundary-scan, Altera ByteBlaster compatible —
Configuration Non-volatile EEPROM (instant-on, no boot PROM) —
RoHS Status ROHS3 Compliant (per fpgalink listing) [DATA_NEEDED: RoHS compliance status]
Moisture Sensitivity Level (MSL) MSL-3, 168 hours (per fpgalink listing) —
Manufacturer Lead Time 1-7 days (per fpgalink listing) —
Series — MAX 9000
Logic Family — CMOS (EEPROM-based)
Device Type — CPLD (Complex Programmable Logic Device)
User I/Os — 60
Number of Pins — 84
Package Type — Plastic Leaded Chip Carrier (PLCC-84, J-bend)
Package Code — QCCJ
Propagation Delay (tPD) — 16 ns
Internal Frequency — 118 MHz
Programming — 5.0-V In-System Programmable via JTAG (IEEE 1149.1)
Terminal Form — J BEND
MSL Level — [DATA_NEEDED: MSL moisture sensitivity level]

Datasheets & Resources

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