EPM9320LC84-20N - 320-Cell MAX 9000 CPLD, 84-PLCC | Intel / Altera
MPN: EPM9320LC84-20N β Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $18.75 | $18.75 |
| 10 | $16.4 | $164.00 |
| 100 | $13.95 | $1,395.00 |
| 500 | $11.8 | $5,900.00 |
| 1,000 | $10.25 | $10,250.00 |
Drop-in alternatives for EPM9320LC84-20N β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
EPM9320LC84-15
β Drop-Inβ In Stock
$17.95 / Unit
View Datasheet βEPM9320LC84-10
β Drop-Inβ In Stock
$84.96 / Unit
View Datasheet βEPM9320LC84-20
β Drop-Inβ In Stock
$9.75 / Unit
View Datasheet βEPM9320LI84-20
β Drop-Inβ In Stock
$12.8 / Unit
View Datasheet βEPM9320LI84-10N
β Drop-Inπ Reference alternative (not in catalog)
EPM9320ALI84-10N
β Drop-Inβ In Stock
$21.95 / Unit
View Datasheet βEPM9320LC84-20N Maximum Ratings & Electrical Characteristics
| Series | MAX 9000 |
| Logic Family | CMOS (EEPROM-based) |
| Device Type | CPLD (Complex Programmable Logic Device) |
| Usable Gates | 6,000 |
| Macrocells | 320 |
| User I/Os | 60 |
| Number of Pins | 84 |
| Package Type | Plastic Leaded Chip Carrier (PLCC-84, J-bend) |
| Package Code | QCCJ |
| Propagation Delay (tPD) | 16 ns |
| Internal Frequency | 118 MHz |
| Supply Voltage (VCC) | 5 V |
| Operating Temperature | 0 C to +70 C (Commercial) |
| Programming | 5.0-V In-System Programmable via JTAG (IEEE 1149.1) |
| Mounting Type | Surface Mount (J-bend) |
| Terminal Form | J BEND |
EPM9320LC84-20N Pin Configuration
| Pin 1 | I/O β User I/O pin (bank 1) |
| Pin 2 | I/O β User I/O pin (bank 1) |
| Pin 3 | I/O β User I/O pin (bank 1) |
| Pin 4 | I/O β User I/O pin (bank 1) |
| Pin 5 | I/O β User I/O pin (bank 1) |
| Pin 6 | I/O β User I/O pin (bank 1) |
| Pin 7 | I/O β User I/O pin (bank 1) |
| Pin 8 | I/O β User I/O pin (bank 1) |
| Pin 9 | I/O β User I/O pin (bank 1) |
| Pin 10 | I/O β User I/O pin (bank 1) |
| Pin 11 | I/O β User I/O pin (bank 1) |
| Pin 12 | GND β Ground |
| Pin 13 | I/O β User I/O pin (bank 2) |
| Pin 14 | I/O β User I/O pin (bank 2) |
| Pin 15 | I/O β User I/O pin (bank 2) |
| Pin 16 | I/O β User I/O pin (bank 2) |
| Pin 17 | I/O β User I/O pin (bank 2) |
| Pin 18 | I/O β User I/O pin (bank 2) |
| Pin 19 | I/O β User I/O pin (bank 2) |
| Pin 20 | I/O β User I/O pin (bank 2) |
| Pin 21 | I/O β User I/O pin (bank 2) |
| Pin 22 | I/O β User I/O pin (bank 2) |
| Pin 23 | VCC β +5 V supply |
| Pin 24 | I/O β User I/O pin (bank 2) |
| Pin 25 | I/O β User I/O pin (bank 2) |
| Pin 26 | I/O β User I/O pin (bank 2) |
| Pin 27 | I/O β User I/O pin (bank 2) |
| Pin 28 | I/O β User I/O pin (bank 2) |
| Pin 29 | I/O β User I/O pin (bank 2) |
| Pin 30 | TDI β JTAG Test Data In |
| Pin 31 | TMS β JTAG Test Mode Select |
| Pin 32 | TCK β JTAG Test Clock |
| Pin 33 | I/O β User I/O pin (bank 3) |
| Pin 34 | I/O β User I/O pin (bank 3) |
| Pin 35 | I/O β User I/O pin (bank 3) |
| Pin 36 | I/O β User I/O pin (bank 3) |
| Pin 37 | I/O β User I/O pin (bank 3) |
| Pin 38 | I/O β User I/O pin (bank 3) |
| Pin 39 | I/O β User I/O pin (bank 3) |
| Pin 40 | I/O β User I/O pin (bank 3) |
| Pin 41 | I/O β User I/O pin (bank 3) |
| Pin 42 | GND β Ground |
| Pin 43 | I/O β User I/O pin (bank 4) |
| Pin 44 | I/O β User I/O pin (bank 4) |
| Pin 45 | I/O β User I/O pin (bank 4) |
| Pin 46 | I/O β User I/O pin (bank 4) |
| Pin 47 | I/O β User I/O pin (bank 4) |
| Pin 48 | I/O β User I/O pin (bank 4) |
| Pin 49 | I/O β User I/O pin (bank 4) |
| Pin 50 | I/O β User I/O pin (bank 4) |
| Pin 51 | I/O β User I/O pin (bank 4) |
| Pin 52 | I/O β User I/O pin (bank 4) |
| Pin 53 | I/O β User I/O pin (bank 4) |
| Pin 54 | VCC β +5 V supply |
| Pin 55 | I/O β User I/O pin (bank 4) |
| Pin 56 | I/O β User I/O pin (bank 4) |
| Pin 57 | I/O β User I/O pin (bank 4) |
| Pin 58 | I/O β User I/O pin (bank 4) |
| Pin 59 | I/O β User I/O pin (bank 4) |
| Pin 60 | I/O β User I/O pin (bank 4) |
| Pin 61 | I/O β User I/O pin (bank 5) |
| Pin 62 | I/O β User I/O pin (bank 5) |
| Pin 63 | GND β Ground |
| Pin 64 | I/O β User I/O pin (bank 5) |
| Pin 65 | I/O β User I/O pin (bank 5) |
| Pin 66 | I/O β User I/O pin (bank 5) |
| Pin 67 | I/O β User I/O pin (bank 5) |
| Pin 68 | I/O β User I/O pin (bank 5) |
| Pin 69 | I/O β User I/O pin (bank 5) |
| Pin 70 | I/O β User I/O pin (bank 5) |
| Pin 71 | I/O β User I/O pin (bank 5) |
| Pin 72 | I/O β User I/O pin (bank 5) |
| Pin 73 | I/O β User I/O pin (bank 5) |
| Pin 74 | I/O β User I/O pin (bank 5) |
| Pin 75 | VCC β +5 V supply |
| Pin 76 | I/O β User I/O pin (bank 6) |
| Pin 77 | I/O β User I/O pin (bank 6) |
| Pin 78 | I/O β User I/O pin (bank 6) |
| Pin 79 | I/O β User I/O pin (bank 6) |
| Pin 80 | I/O β User I/O pin (bank 6) |
| Pin 81 | I/O β User I/O pin (bank 6) |
| Pin 82 | I/O β User I/O pin (bank 6) |
| Pin 83 | TDO β JTAG Test Data Out |
| Pin 84 | I/O β User I/O pin (bank 6) |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM9320LC84-20N is suitable for 6 applications: Address Decoding & Bus Interface Logic, Glue Logic Replacement for Discrete TTL, Industrial Control Board Logic, State Machine & Sequencer Implementation, Legacy Microcontroller I/O Expansion, Telecom Backplane & Bus Arbitration.
Address Decoding & Bus Interface Logic
The EPM9320LC84-20N is widely deployed as the central address decoder and bus-interface glue between microprocessors, memory, and peripherals in legacy embedded boards. Its 60 user I/Os and 320 macrocells provide enough logic capacity to decode a full 24-bit address bus plus generate chip-select strobes for SRAM, ROM, and peripheral banks. The 16 ns tPD ensures clean chip-select timing at system clock rates up to ~60 MHz, well matched to 8051, 68k, and early ARM7 designs. Unlike an FPGA, the CPLD's deterministic timing means the chip-select setup and hold are guaranteed regardless of design density, removing a key verification burden for the hardware engineer.
Recommended
Glue Logic Replacement for Discrete TTL
Engineers use the EPM9320LC84-20N to consolidate dozens of 74LS, 74HC, and 74FTTL packages into a single 5-V tolerant CPLD, dramatically reducing board area and BOM cost. With 320 macrocells equivalent to roughly 50-80 standard TTL gates per macrocell, the device can absorb entire address-latch, bus-buffer, and interrupt-controller sub-systems. The 5-V native I/Os interface directly to legacy peripherals without level shifters, and the in-system programmability allows last-minute logic fixes without board re-spin. Compared to a discrete TTL implementation, the CPLD reduces power, improves noise margin, and provides testable JTAG access to internal nodes.
Recommended
Industrial Control Board Logic
In industrial control cabinets, the EPM9320LC84-20N serves as the deterministic logic core that processes sensor inputs, drives relay and MOSFET control outputs, and sequences power-up events. Its commercial 0C to +70C temperature range fits most factory-floor enclosures, while the industrial -LI84-20 variant extends to -40C to +85C for outdoor installations. The 60 I/Os handle multiple encoder, limit-switch, and optocoupler interfaces in parallel, and the EEPROM-based configuration retains logic state across power cycles for fail-safe recovery. Compared with microcontrollers, the CPLD's predictable timing is preferred for safety-critical interlock logic where software timing variance is unacceptable.
Recommended
State Machine & Sequencer Implementation
The EPM9320LC84-20N is well suited to implementing complex multi-state control sequencers for power-supply start-up, motor commutation, and protocol handshaking. With 320 macrocells the device can hold 20-30 large state machines simultaneously, each guaranteed by the MAX 9000 deterministic timing model. The 16 ns tPD provides 60 MHz+ state-transition bandwidth, sufficient for high-speed serial protocol state machines (UART, SPI, I2C master). Non-volatile EEPROM configuration ensures the state machine resumes correctly after power-loss without external boot memory. This application pattern is common in telecom and instrumentation designs.
Recommended
Legacy Microcontroller I/O Expansion
Designers use the EPM9320LC84-20N to add 60 extra 5-V tolerant I/Os to older microcontrollers that have insufficient native pins, eliminating the need for external I/O expander ICs with limited drive strength. The CPLD's 5-V I/O compatibility matches 8051, PIC, and AVR MCU families directly without level translation, and its high-drive outputs can sink/source 24 mA per pin for LED and relay driving. The in-system programmability via JTAG lets engineers iterate on the I/O map during development. Compared with SPI/I2C I/O expanders, the CPLD provides parallel latency (one clock cycle) instead of serial round-trip delays.
Recommended
Telecom Backplane & Bus Arbitration
The EPM9320LC84-20N is used in telecom backplanes to arbitrate multiple bus masters, generate timing strobes, and provide bus-isolation logic between redundant control cards. Its 60 I/Os are sufficient for one full bus-arbitration tree plus status and interrupt fan-out, and the 16 ns tPD meets typical 50 MHz backplane timing budgets with margin. The 5-V tolerance integrates seamlessly with legacy ECL/TTL backplane circuitry, while the JTAG port enables in-field reconfiguration for protocol upgrades. Compared with an FPGA, the CPLD's instant-on (no boot time) and deterministic timing are preferred for hot-swap and failover scenarios.
Recommended
Recommended Products Summary
Engineering reference data for EPM9320LC84-20N β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM9320LC84-15 | EPM9320LC84-10 | EPM9320LC84-20 | EPM9320LI84-20 | EPM9320LI84-10N | EPM9320ALI84-10N |
|---|---|---|---|---|---|---|---|
| Package | PLCC-84 (QCCJ) | PLCC-84 (QCCJ) - same | PLCC-84 (QCCJ) - same | PLCC-84 (QCCJ) - same | PLCC-84 (QCCJ) - same | PLCC-84 (QCCJ) - same | PLCC-84 (QCCJ) - same |
| Brand | Intel | Intel | Intel | Intel | Intel | Intel | Intel |
| Propagation Delay (tPD) | 16 ns | 15 ns | 10 ns | 16 ns (identical) | 16 ns | 10 ns | 10 ns |
| Internal Frequency | 118 MHz | 125 MHz | 148 MHz | 118 MHz | 118 MHz | 148 MHz | 148 MHz |
| Macrocells | 320 | 320 | 320 | 320 | 320 | 320 | 320 |
| User I/Os | 60 | 60 | 60 | 60 | 60 | 60 | 60 |
| Operating Temperature | 0 C to +70 C (Commercial) | 0 C to +70 C (Commercial) | 0 C to +70 C (Commercial) | 0 C to +70 C (Commercial) | -40 C to +85 C (Industrial) | -40 C to +85 C (Industrial) | -40 C to +85 C (Industrial) |
| Lead-Free / RoHS | Yes (N suffix) | Varies by suffix | Varies by suffix | No (leaded) | No (leaded) | Yes (N suffix) | Yes (N suffix) |
| Supply Voltage | 5 V | 5 V | 5 V | 5 V | 5 V | 5 V | 5 V |
Key Differentiators
- RoHS-compliant lead-free terminal finish (vs EPM9320LC84-20)
- Drop-in upgrade path to higher speed grades (vs EPM9320LC84-15)
- Industrial-temperature variant available in same footprint (vs EPM9320LI84-20)
- 320 macrocells in a single 5-V device vs. lower-density competitors (vs Generic 5-V CPLD alternatives)
Design Notes
The EPM9320LC84-20N requires a stable 5.0 V +/- 5% supply. Place a 0.1 uF ceramic decoupling capacitor as close as possible to each of the four VCC pins (12, 23, 54, 75) and one bulk 10-47 uF tantalum or low-ESR electrolytic capacitor near the package. Multiple VCC/GND pairs reduce ground bounce and improve JTAG programming reliability. According to the manufacturer datasheet, inrush current during JTAG programming peaks at ~150 mA per VCC pin, so power-trace widths should be at least 0.5 mm to avoid IR drop.
The 84-pin PLCC socket should be a low-profile through-hole type with J-bend receptacle to match the LC84 outline. For surface-mount assembly, use a PLCC-84 SMT socket rather than direct soldering - hand rework of direct-soldered PLCC is extremely difficult. Maintain at least 8 mil trace/space for the I/O fan-out and reserve a 2-mm keep-out under the package for thermal relief pads. Group I/O banks together on the PCB to simplify routing, since the MAX 9000 architecture restricts some pin functions to specific bank locations.
Do not confuse the EPM9320LC84-20N (commercial, lead-free) with the EPM9320LC84-20 (commercial, leaded) or the EPM9320LI84-20 (industrial) at procurement - the suffix N and L carry both environmental and temperature-grade implications. Always verify the JTAG chain pinout: TMS, TCK, TDI, TDO must be pulled to known states (typically 10 kohm pull-up on TMS/TCK/TDI) when not in use, or the device may enter unintended test modes at power-up. Finally, ensure your programmer supports the MAX 9000 family - older third-party programmers may require a 'device signature' update to recognize the -20N variant.
The 60 user I/Os on the EPM9320LC84-20N can drive 24 mA per pin at 5 V, making them suitable for direct LED and opto-coupler drive. However, for high-speed signals above 50 MHz, add 22-33 ohm series-termination resistors at the CPLD output to dampen transmission-line reflections. The MAX 9000 output edge rates are ~1-2 ns, so treat all output traces longer than 25 mm as transmission lines. Keep clock and JTAG traces short and away from I/O switching lines to minimize crosstalk into the programming logic.
Compliance Information
Lead-free per N suffix in part number. RoHS compliance based on Intel/Altera lead-free terminal finish designation; verified by 'N' suffix convention. AEC-Q100 not applicable for CPLD in commercial/industrial use. Halogen-free status not specifically listed in available data - left as unknown per data-authenticity rule.
