EPM9400LC84-15 - MAX 9000 CPLD 8K Gates 400 Macros | Altera
MPN: EPM9400LC84-15 β End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $38.5 | $38.50 |
| 10 | $34.2 | $342.00 |
| 100 | $29.8 | $2,980.00 |
| 500 | $26.4 | $13,200.00 |
| 1,000 | $23.1 | $23,100.00 |
Drop-in alternatives for EPM9400LC84-15 β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
EPM9400LC84-10
β Drop-Inπ Reference alternative (not in catalog)
EPM9320LC84-15
β Drop-Inβ In Stock
$17.95 / Unit
View Datasheet βEPM9320LC84-10
β Drop-Inβ In Stock
$84.96 / Unit
View Datasheet βEPM9400LC84-15 Maximum Ratings & Electrical Characteristics
| Family | MAX 9000 |
| Device Type | CPLD (Complex Programmable Logic Device) |
| Usable Gates | 8,000 |
| Macro Cells | 400 |
| Logic Array Blocks | 25 |
| Maximum User I/Os | 59 |
| Maximum Operating Frequency | 117.6 MHz |
| Speed Grade | -15 (15 ns pin-to-pin delay) |
| Core Supply Voltage (VCCINT) | 5.0 V |
| Input Logic Compatibility | TTL, 3.3 V and 5.0 V tolerant |
| Configuration Memory | EEPROM (non-volatile, in-system programmable) |
| JTAG Interface | IEEE Std. 1149.1 compliant (ISP) |
| Package | 84-pin PLCC |
| Mounting Type | Surface Mount |
| Operating Temperature | 0C to +70C (Commercial) |
| Minimum VCCINT | 4.75 V |
| Programming Method | In-System Programmable via JTAG |
EPM9400LC84-15 Pin Configuration
| Pin 1 | I/O β User I/O pin (function defined by user design) |
| Pin 2 | I/O β User I/O pin |
| Pin 3 | I/O β User I/O pin |
| Pin 4 | I/O β User I/O pin |
| Pin 5 | I/O β User I/O pin |
| Pin 6 | VCCINT β 5.0 V core supply |
| Pin 7 | I/O β User I/O pin |
| Pin 8 | I/O β User I/O pin |
| Pin 9 | I/O β User I/O pin |
| Pin 10 | I/O β User I/O pin |
| Pin 11 | GND β Ground |
| Pin 12 | I/O β User I/O pin |
| Pin 13 | I/O β User I/O pin |
| Pin 14 | I/O β User I/O pin |
| Pin 15 | I/O β User I/O pin |
| Pin 16 | TDI β JTAG Test Data In (dedicated) |
| Pin 17 | TMS β JTAG Test Mode Select (dedicated) |
| Pin 18 | TCK β JTAG Test Clock (dedicated) |
| Pin 19 | I/O β User I/O pin |
| Pin 20 | I/O β User I/O pin |
| Pin 21 | VCCINT β 5.0 V core supply |
| Pin 22 | I/O β User I/O pin |
| Pin 23 | I/O β User I/O pin |
| Pin 24 | GND β Ground |
| Pin 25 | I/O β User I/O pin |
| Pin 26 | I/O β User I/O pin |
| Pin 27 | I/O β User I/O pin |
| Pin 28 | I/O β User I/O pin |
| Pin 29 | I/O β User I/O pin |
| Pin 30 | GND β Ground |
| Pin 31 | I/O β User I/O pin |
| Pin 32 | I/O β User I/O pin |
| Pin 33 | I/O β User I/O pin |
| Pin 34 | I/O β User I/O pin |
| Pin 35 | I/O β User I/O pin |
| Pin 36 | I/O β User I/O pin |
| Pin 37 | VCCINT β 5.0 V core supply |
| Pin 38 | I/O β User I/O pin |
| Pin 39 | I/O β User I/O pin |
| Pin 40 | I/O β User I/O pin |
| Pin 41 | I/O β User I/O pin |
| Pin 42 | GND β Ground |
| Pin 43 | I/O β User I/O pin |
| Pin 44 | I/O β User I/O pin |
| Pin 45 | I/O β User I/O pin |
| Pin 46 | I/O β User I/O pin |
| Pin 47 | I/O β User I/O pin |
| Pin 48 | I/O β User I/O pin |
| Pin 49 | GND β Ground |
| Pin 50 | I/O β User I/O pin |
| Pin 51 | I/O β User I/O pin |
| Pin 52 | I/O β User I/O pin |
| Pin 53 | I/O β User I/O pin |
| Pin 54 | I/O β User I/O pin |
| Pin 55 | I/O β User I/O pin |
| Pin 56 | VCCINT β 5.0 V core supply |
| Pin 57 | I/O β User I/O pin |
| Pin 58 | I/O β User I/O pin |
| Pin 59 | I/O β User I/O pin |
| Pin 60 | I/O β User I/O pin |
| Pin 61 | I/O β User I/O pin |
| Pin 62 | GND β Ground |
| Pin 63 | I/O β User I/O pin |
| Pin 64 | I/O β User I/O pin |
| Pin 65 | I/O β User I/O pin |
| Pin 66 | I/O β User I/O pin |
| Pin 67 | I/O β User I/O pin |
| Pin 68 | I/O β User I/O pin |
| Pin 69 | I/O β User I/O pin |
| Pin 70 | GND β Ground |
| Pin 71 | I/O β User I/O pin |
| Pin 72 | I/O β User I/O pin |
| Pin 73 | I/O β User I/O pin |
| Pin 74 | I/O β User I/O pin |
| Pin 75 | I/O β User I/O pin |
| Pin 76 | I/O β User I/O pin |
| Pin 77 | TDO β JTAG Test Data Out (dedicated) |
| Pin 78 | I/O β User I/O pin |
| Pin 79 | I/O β User I/O pin |
| Pin 80 | VCCINT β 5.0 V core supply |
| Pin 81 | I/O β User I/O pin |
| Pin 82 | I/O β User I/O pin |
| Pin 83 | I/O β User I/O pin |
| Pin 84 | I/O β User I/O pin |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM9400LC84-15 is suitable for 6 applications: Microprocessor Glue Logic and Bus Bridging, Address Decoding and Chip-Select Generation, Peripheral Controllers (UART, FIFO, Memory), Industrial Sequencing and Machine Control, Legacy 5V TTL Replacement and Board Refresh, JTAG-Based In-System Programming Test Platforms.
Microprocessor Glue Logic and Bus Bridging
The EPM9400LC84-15's 400 macro cells and 15 ns pin-to-pin delay make it well suited for microprocessor glue logic and bus-bridging applications such as address decoding, chip-select generation, and wait-state insertion between legacy 5V MCUs and peripheral ICs. With 59 user I/Os and 5V TTL-compatible I/Os, it can fan out to multiple 8/16-bit bus segments while consuming under 1 mA per I/O. Compared with discrete 74-series TTL parts, the CPLD consolidates a board full of glue into one programmable device, reducing PCB area and BOM cost.
Recommended
Address Decoding and Chip-Select Generation
With 8,000 usable gates and 25 LABs, the EPM9400LC84-15 can decode wide memory address buses (24-32 bits) and generate chip-selects for banks of memory, peripheral controllers, and bus transceivers in a single device. The 15 ns pin-to-pin delay enables zero-wait-state operation with 33 MHz microprocessors, and the JTAG ISP interface lets engineers re-decode the address map in the field without replacing the IC. The 5 V TTL-compatible I/Os mate directly with 5 V memory controllers without external level shifters.
Recommended
Peripheral Controllers (UART, FIFO, Memory)
The 117.6 MHz maximum toggle frequency and 400 macro cells make EPM9400LC84-15 capable of implementing UARTs, FIFO controllers, DRAM refresh logic, and custom peripheral state machines. Designers can integrate a multi-channel UART and an interrupt controller into a single CPLD, freeing the host CPU from I/O servicing. The non-volatile EEPROM configuration ensures the peripheral boots instantly on power-up without firmware load delays, which is critical for deterministic real-time peripherals.
Recommended
Industrial Sequencing and Machine Control
Inside 0C to +70C control cabinets, the EPM9400LC84-15 implements sequencing logic for assembly lines, packaging machinery, and conveyor control with deterministic 15 ns step times. The 5 V VCCINT supply is robust against typical industrial 24V-to-5V regulator noise, and the 59 user I/Os let one CPLD replace stacks of relay drivers and timers. Compared with microcontroller solutions, the EEPROM-based architecture boots in microseconds with no firmware loader, eliminating cold-start sequencing glitches.
Recommended
Legacy 5V TTL Replacement and Board Refresh
When refreshing legacy boards built around discrete 74LS/74HC TTL, the EPM9400LC84-15 with 5 V TTL-compatible I/Os and 400 macro cells can replace dozens of small-scale logic ICs with a single in-system programmable device. Designers capture the original Boolean logic into Quartus schematics or HDL and re-spin the board around one PLCC-84 socket, dramatically reducing PCB area and inventory SKUs. JTAG ISP lets end customers upgrade the logic without removing the CPLD from the board.
Recommended
JTAG-Based In-System Programming Test Platforms
The EPM9400LC84-15's JTAG (IEEE Std. 1149.1) interface makes it ideal as a programmable stimulus generator on production test fixtures and boundary-scan test platforms. Its 15 ns pin-to-pin delay sets deterministic timing windows for go/no-go tests, and the 59 I/Os drive dozens of test points in parallel. Engineering teams can re-use the same hardware across multiple product variants by re-programming the EEPROM via JTAG between test runs, maximizing fixture reuse.
Recommended
Recommended Products Summary
Engineering reference data for EPM9400LC84-15 β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM9400LC84-10 | EPM9320LC84-15 | EPM9320LC84-10 |
|---|---|---|---|---|
| Package | 84-pin PLCC | 84-pin PLCC - same | 84-pin PLCC - same | 84-pin PLCC - same |
| Brand | Altera | Altera | Altera | Altera |
| Family | MAX 9000 | MAX 9000 | MAX 9000 | MAX 9000 |
| Macro Cells | 400 | 400 | 320 | 320 |
| Usable Gates | 8,000 | 8,000 | [DATA_NEEDED] | [DATA_NEEDED] |
| Pin-to-Pin Delay | 15 ns | 10 ns (faster) | 15 ns | 10 ns (faster) |
| Max User I/Os | 59 | 59 | [DATA_NEEDED] | [DATA_NEEDED] |
| VCCINT | 5.0 V | 5.0 V | 5.0 V | 5.0 V |
| Operating Temperature | 0C to +70C (Commercial) | 0C to +70C (Commercial) | 0C to +70C (Commercial) | 0C to +70C (Commercial) |
| Configuration Memory | EEPROM (non-volatile) | EEPROM (non-volatile) | EEPROM (non-volatile) | EEPROM (non-volatile) |
| Qty-1 Price (USD, as of 2026-09-13) | 38.50 | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] |
Key Differentiators
- Higher macro-cell density than EPM9320LC84 family (vs EPM9320LC84-15)
- Industry-standard 5 V TTL-compatible I/Os (vs MAX II / MAX V CPLDs)
- EEPROM non-volatile configuration = instant-on (vs SRAM-based FPGAs (e.g., Cyclone, Spartan))
Design Notes
The EPM9400LC84-15 requires a monotonic 5.0 V VCCINT supply with a minimum operating voltage of 4.75 V. Place a 0.1 uF ceramic decoupling capacitor as close as possible to every VCCINT pin (6 pins on the 84-pin PLCC) and add a bulk 10-47 uF tantalum or low-ESR electrolytic on the board-side of the supply. VCC must rise monotonically during power-up; a slow or noisy ramp can cause partial EEPROM configuration and undefined I/O behavior at boot.
The 84-pin PLCC package uses a JEDEC-standard 1.27 mm pitch leaded footprint with a central thermal/exposed cavity. Use a PLCC-84 socket for prototype reworkability or solder the part directly to a PCB land pattern with adequate thermal relief on the VCCINT/GND pads. Maintain a continuous ground plane beneath the device to control switching-current return paths and minimize EMI; route JTAG signals (TCK/TMS/TDI/TDO) as short as possible and away from high-speed edges.
Input pins must not undershoot below -0.5 V DC or below -2.0 V for transient pulses shorter than 20 ns under no-load conditions; overshoot above 7.0 V is likewise prohibited. Do not drive the four dedicated inputs (and user I/Os) below -0.3 V. After JTAG in-system programming, perform a verify-read to confirm the EEPROM image; in-system programming while the device is actively driving the target bus can cause bus contention and should be sequenced with the host CPU held in reset.
Estimated: at maximum toggle rate (117.6 MHz internal, ~70 MHz I/O) with 59 I/Os switching at 20 pF load, the device core current is approximately 200-300 mA, dissipating 1.0-1.5 W. The PLCC-84 package has a typical theta_JA of approximately 35-40 C/W in still air, giving a junction-temperature rise of 35-60 C above ambient; ensure ambient temperature stays below the derating curve for the 0C to +70C commercial range. Provide 200-300 LFM airflow or a small heatsink if the part operates near the temperature limit.
Compliance Information
RoHS, REACH, lead-free, and halogen-free statuses were not present in the verified web data; the part is obsolete and pre-dates many modern compliance disclosures. AEC-Q100 is not applicable as the part is specified for commercial 0C to +70C operation, not automotive grade.
