EPM9320LC84-15 vs EPM9320ALC84-15 Comparison

Detailed side-by-side comparison of EPM9320LC84-15 by Intel and EPM9320ALC84-15 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Intel
EPM9320LC84-15

EPM9320LC84-15 - MAX 9000 CPLD 320-Macrocell 84-PLCC | Intel

EPM9320LC84-15 Obsolete

Specification Comparison

Parameter EPM9320LC84-15 EPM9320ALC84-15
Brand Intel Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Nrnd
Stock Status In Stock In Stock
Unit Price (USD) $17.95 $9.95
Family MAX 9000 MAX 9000 CPLD
Series EPM9320 β€”
Device Type CPLD (Complex Programmable Logic Device) β€”
Macrocells 320 320
Usable Gates 6,000 6000
Logic Array Blocks (LABs) 20 16
Propagation Delay (tPD) 15 ns (max) 16 ns
Maximum Clock Frequency 117.6 MHz β€”
Supply Voltage (VCC) 4.75 V to 5.25 V (5.0 V nominal) 4.75 V to 5.25 V (5 V nominal)
Programmability 5.0 V in-system programmable (ISP) via JTAG β€”
JTAG Interface IEEE Std. 1149.1 boundary-scan compliant β€”
Package 84-pin PLCC (Plastic Leaded Chip Carrier) 84-pin PLCC (S-PQCC-J84, J-lead)
Mounting Type Surface Mount Through-hole / socket
Operating Temperature -40C to +85C (commercial) [DATA_NEEDED: exact grade] -40C to +85C (industrial)
Technology CMOS EEPROM-based, third-generation Multiple Array MatriX (MAX) CMOS, EEPROM-based configuration
Built-in Pull-up Resistors Yes, on every I/O pin β€”
Architecture Feature Pin-locking across design iterations β€”
RoHS Status [DATA_NEEDED: confirm from manufacturer] [DATA_NEEDED: rohs status]
User I/O β€” 56
Programming Interface β€” JTAG (IEEE 1149.1) / ISP
Moisture Sensitivity Level (MSL) β€” MSL-3 (168 hours per fpgalink.com)
Lead-Free / Halogen-Free β€” [DATA_NEEDED: lead free status]
RoHS3 Compliance β€” ROHS3 Compliant (per fpgalink.com listing)

Datasheets & Resources

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