EPM9320LI84-20N vs EPM9320ALC84-20 Comparison
Detailed side-by-side comparison of EPM9320LI84-20N by Altera and EPM9320ALC84-20 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM9320LI84-20N | EPM9320ALC84-20 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Nrnd |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $9.75 | $10.50 |
| Family | MAX 9000 | MAX 9000 |
| Device Type | CPLD (Complex Programmable Logic Device) | EPLD (Erasable Programmable Logic Device) |
| Macrocells | 320 | 320 |
| Usable Gates | 6,000 to 12,000 | β |
| User I/O Pins | 60 | β |
| Total Pins | 84 | β |
| Package | PLCC-84 (Plastic Leaded Chip Carrier, J-lead) | PLCC-84 |
| Propagation Delay (tPD) | 20 ns (speed grade -20) | β |
| Pin-to-Pin Delay | 16 ns (per DigChip spec block) | β |
| Maximum Counter Frequency | 118 MHz | β |
| Logic Family | CMOS, EEPROM-based | β |
| Supply Voltage | 5.0 V | 5.0 V |
| Operating Temperature | 0 C to +70 C (commercial) | [DATA_NEEDED: commercial or industrial grade] |
| Programming Interface | IEEE 1149.1 JTAG, in-system programmable | β |
| Architecture | Multiple Array MatriX (MAX) - third generation | β |
| Process Technology | Advanced CMOS EEPROM | 0.5 Β΅m CMOS EEPROM |
| RoHS Status | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: per Altera datasheet] |
| Logic Array Blocks (LABs) | β | 16 |
| Maximum User I/Os | β | 212 |
| Pin-to-Pin Delay (tPD) | β | 20 ns |
| Programmability | β | In-system via IEEE 1149.1 JTAG |
| Mounting Type | β | Surface Mount (PLCC socket compatible) |
| Configuration Memory | β | Non-volatile EEPROM |
| Boundary Scan | β | JTAG IEEE 1149.1 |
| Design Software | β | MAX+PLUS II / Quartus II (legacy) |